PRELIMINARY
CY2283
Pentium®/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for
Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs
SDRAM outputs in place of the CY2283 and can be placed in
Features
close proximity to the SDRAM modules.
• Mixed 2.5V and 3.3V operation
The CY2283 possesses power-down, CPU stop, and PCI stop
pins for power management control. These inputs are multi-
plexed with SDRAM clock outputs, and are selected when the
MODE pin is driven LOW. Additionally, the signals are synchro-
nized on-chip, and ensure glitch-free transitions on the out-
puts. When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is assert-
ed, the PCI clock outputs (except the free-running PCI clock)
are driven LOW. When the PWR_DWN pin is asserted, the
reference oscillator and PLLs are shut down, and all outputs
are driven LOW.
• Complete clock solution for Pentium® /II, Cyrix 6x86,
and AMD K6 processor-based motherboards
— Four CPU clocks at 2.5V or 3.3V
[1]
— Twelve 3.3V SDRAM clocks
— Five synchronous PCI clocks, one free-running
— One 3.3V 48 MHz USB clock
— One 3.3V Ref. clock at 14.318 MHz
— Two AGP clocks at 3.3V
• Support for ALI (-1 option) and VIA (-2 option)
2
• I C™ Serial Configuration Interface
• Full EMI control with factory-EPROM programmable
output drive and slew rate
• Factory-EPROM programmable CPU clock frequencies
for custom configurations
The CY2283 outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
• Power-down, CPU stop, and PCI stop pins
• Available in space-saving 48-pin SSOP package
CY2283 Selector Guide
Functional Description
The CY2283 is a clock Synthesizer/Driver for Pentium, Cyrix,
or AMD processor-based PCs using the ALI Aladdin V (-1 op-
tion) or VIA MVP3 (-2 option) chipset.
Clock Outputs
CPU (66.6, 75, 83.3, 100MHz)
SDRAM
-1 (ALI V) -2 (VIA MVP3)
4
4
[1]
12
12
[2]
[2]
The CY2283 outputs four CPU clocks at 2.5V or 3.3V. There
are five PCI clocks, running at 30 or 33.3 MHz. One of the PCI
clocks is free-running. Additionally, the part outputs twelve
3.3V SDRAM clocks , one 3.3V USB clock at 48 MHz, and
one 3.3V reference clock at 14.318 MHz. Finally, the part out-
puts two AGP clocks running at 66.66 MHz or 60 MHz.
PCI (30, 33.3 MHz)
USB (48MHz)
5
5
1
1
[1]
AGP (66.6, 60MHz)
Ref. (14.318 MHz)
CPU-PCI delay
2
1
2
1
2.5−5.5 ns
2.5−5.5 ns
The CY2283 has the flexibility to work as either a one-chip or
as part of a two-chip clocking solution. In 100-MHz board de-
signs based on the ALI Aladdin V chipset, it is recommended
that the CY2283 be used with an external SDRAM buffer so-
lution such as the CY2318NZ or CY2314NZ. In this configura-
tion the SDRAM outputs on the CY2283 must be either turned
AGP clock
In phase
with PCI
In phase
with CPU
Notes:
1. SDRAM clocks available up to 83.3MHz. In 100-MHz designs based on the
ALI V chipset, an external CY231xNZ buffer should be used.
2. One free-running PCI clock
2
off using I C or left floating. The CY231xNZ family provides the
Pin Configuration (48 SSOP)
Logic Block Diagram
REF0 (14.318 MHz)
XTALIN
AV
DD
V
1
2
3
4
48
47
46
14.318
DDQ3
MHz
REF0
USBCLK
SEL1
OSC.
XTALOUT
V
SS
STOP
CPU
PLL
CPUCLK [0-3]
VDDCPU
LOGIC
XTALIN
45
44
43
42
41
V
SS
5
6
7
XTALOUT
CPUCLK0
CPUCLK1
V
V
DDQ3
PCICLK_F
PCICLK0
DDCPU
SEL0
SEL1
SDRAM5/PWR_DWN
SDRAM [0-4],[8-11]
EPROM
CPUCLK2
CPUCLK3
8
V
SS
9
40
39
38
10
11
12
PCICLK1
PCICLK2
PCICLK3
SDRAM6/CPU_STOP
V
SS
MODE
SDRAM0
SDRAM1
V
37
36
35
34
Delay (-2 option)
13
AGP0
DDQ3
SDRAM7/PCI_STOP
AGP
SYS PLL
V
DDQ3
14
15
16
17
18
SDRAM2
SDRAM3
/1, /1.25, /1.5
Delay (-1 option)
/2
AGP1
V
33
32
31
30
29
28
27
26
25
SS
V
SS
SDRAM11
SDRAM10
SDRAM4
SDRAM5/PWR_DWN
STOP
LOGIC
PCI [0-3]
PCICLK_F
USBCLK
V
19
20
21
22
23
24
DDQ3
V
DDQ3
SDRAM9
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
SDRAM8
SERIAL
SCLK
V
SS
V
INTERFACE
CONTROL
LOGIC
SS
SDATA
SCLK
SEL0
SDATA
MODE
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 12, 1998