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CY2280PVC-13S PDF预览

CY2280PVC-13S

更新时间: 2024-11-25 21:21:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
11页 177K
描述
Processor Specific Clock Generator, 100MHz, CMOS, PDSO48, SSOP-48

CY2280PVC-13S 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82其他特性:REQUIRES 2.5V SUPPLY VOLTAGE
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.875 mm端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:100 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:2.5,3.3 V主时钟/晶体标称频率:14.318 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Clock Generators最大压摆率:270 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

CY2280PVC-13S 数据手册

 浏览型号CY2280PVC-13S的Datasheet PDF文件第2页浏览型号CY2280PVC-13S的Datasheet PDF文件第3页浏览型号CY2280PVC-13S的Datasheet PDF文件第4页浏览型号CY2280PVC-13S的Datasheet PDF文件第5页浏览型号CY2280PVC-13S的Datasheet PDF文件第6页浏览型号CY2280PVC-13S的Datasheet PDF文件第7页 
PRELIMINARY  
CY2280  
100-MHz Pentium® II Clock Synthesizer/Driver with  
Spread Spectrum for Mobile or Desktop PCs  
Functional Description  
Features  
• Mixed 2.5V and 3.3V operation  
• Clock solution for Pentium® II, and other similar pro-  
cessor-based motherboards  
The CY2280 is a Spread Spectrum clock synthesizer/driver for  
a Pentium II, or other similar processor-based PC requiring  
100-MHz support. All of the required system clocks are provid-  
ed in a space saving 48-pin SSOP package. The CY2280 can  
be used with the CY231x for a total solution for systems with  
SDRAM.  
The CY2280 provides the option of spread spectrum clocking  
on the CPU and PCI clocks for reduced EMI. A downspread  
percentage is introduced when the SEL_SS input is asserted.  
The device can be run without spread spectrum when the  
SEL_SS input is deasserted. The percentage of spreading is  
EPROM-programmable to optimize EMI-reduction.  
— Four 2.5V CPU clocks up to 100 MHz  
— Eight 3.3V synch. PCI clocks, one free-running  
— Two 3.3V 48-MHz USB clocks  
— Three 3.3V Ref. clocks at 14.318 MHz  
— Two 2.5V APIC clocks at 14.318 MHz or PCI/2  
• EMI control  
— Spread spectrum clocking  
— Factory-EPROM programmable spread spectrum  
margin  
The CY2280 has power-down, CPU stop, and PCI stop pins  
for power management control. The signals are synchronized  
on-chip, and ensure glitch-free transitions on the outputs.  
When the CPU_STOP input is asserted, the CPU clock out-  
puts are driven LOW. When the PCI_STOP input is asserted,  
the PCI clock outputs (except the free-running PCI clock) are  
driven LOW. When the PWR_DWN pin is asserted, the refer-  
ence oscillator and PLLs are shut down, and all outputs are  
driven LOW.  
Factory-EPROM programmable output drive and  
slew rate  
• Factory-EPROM programmable CPU clock frequencies  
for custom configurations  
• Available in space-saving 48-pin SSOP package  
CY2280 Selector Guide  
CY2280 Configuration Options  
Clock Outputs  
CPU (66.6, 100 MHz)  
PCI (CPU/2, CPU/3)  
USB (48 MHz)  
-1  
-11S  
-12S  
-13S  
-21S  
-31S  
4
4
4
4
4
4
8
8
8
8
8
8
2
2
2
2
2
2
APIC (14.318 MHz)  
APIC (PCI/2)  
2
2
2
2
--  
2
2
--  
--  
--  
--  
--  
Reference (14.318 MHz)  
CPU-PCI delay  
3
1.54.0 ns  
--  
3
1.54.0 ns  
--  
3
1.54.0 ns  
--  
3
1.54.0 ns  
--  
3
3
1.54.0 ns  
2.0-4.5 ns  
0.6%  
0 ns  
--  
CPU-APIC delay  
Spread Spectrum  
(Downspread)  
N/A  
0.6%  
1.0%  
1.5%  
0.6%  
Logic Block Diagram  
-1  
-2  
APIC [0:1]  
VDDAPIC  
CPU_STOP  
XTALIN  
REF [0-2]  
14.318  
MHz  
OSC.  
VDDREF  
XTALOUT  
STOP  
LOGIC  
CPU  
PLL  
CPUCLK [0-3]  
VDDCPU  
Divider  
Delay  
PWR_DWN  
PCICLK_F  
VDDPCI  
SEL0  
SEL1  
EPROM  
SEL100  
SEL_SS  
STOP  
LOGIC  
PCI [1-7]  
VDDPCI  
PCI_STOP  
SYS PLL  
USBCLK [0:1]  
VDDUSB  
Pentium is a registered trademark of Intel Corporation.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
December 24, 1998  

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