Datasheet > CY22800-145A

CY22800-145A

更新时间： 2024-11-25 04:37:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器 PC
页数	文件大小	规格书
10页	547K
描述
Universal Programmable Clock Generator (UPCG)

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数据手册

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CY22800-145A 数据手册

CY22800

Universal Programmable Clock

Generator (UPCG)

Features

Benefits

• Spread Spectrum, VCXO, and Frequency Select

• Input frequency range:

• Inventoryofonlyonedevice, CY22800, isneededinvarious

applications such as HDTV, STB, DVDR, etc.

• Multiple predefined configurations that can be programmed

into a single chip

— Crystal: 8–30 MHz

— CLKIN: 0.5–100 MHz

• Eliminates the need for expensive and difficult to use

higher-order crystal

• Output frequency:

— Commercial: 1–200 MHz

— Industrial: 1–166 MHz

• Integrated phase-locked loop

• Low jitter, high accuracy outputs

• 3.3V operation

• High-performance PLL tailored for multiple applications

• Meets critical timing requirements in complex system

designs

• Enables application compatibility

• Allows up to three different frequency selects

• 8-pin SOIC package

Logic Block Diagram

Pin Configuration

CY22800

8-pin SOIC

CLKC

XIN/CLKIN

OSC

XOUT

XIN/CLKIN

OUTPUT

DIVIDER

XOUT

VCXO

VCO

CLKB

CLKA

CLKC/FS2/VSS

CLKA/FS0

VDD

FS0/VCXO

VSS

FS2

FS1

FS0

CLKB/FS1

PLL

(with modulation control)

VSS

VDD

Pin Description

Name

Pin Number Description

XIN

Reference Input; Crystal or External Clock

3.3V Voltage Supply

Frequency Select 0/VCXO Analog Control Voltage^[1]

VDD

FS0/VCXO

VSS

Ground

CLKB/FS1

CLKA/FS0

CLKC/FS2/VSS

XOUT

Clock Output B/Frequency Select 1^[1]

Clock Output A/Frequency Select 0^[1]

Clock Output C/Frequency Select 2/VSS^[1]

Reference Output (No Connect when the reference is a clock)

Note

1. Pin definition changes for different configurations. Refer to the specific one-page data sheet for more details.

Cypress Semiconductor Corporation

Document #: 001-07704 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 11, 2007

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