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CY2277A

更新时间： 2024-11-18 04:37:55
品牌 Logo 应用领域
SPECTRALINEAR 驱动器PC时钟
页数 文件大小 规格书
18页 293K
描述
Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel㈢ 82430TX and 2 DIMMs or 3 SO-DIMMs

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CY2277A 数据手册

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Y2277A  
CY2277A  
Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/  
Mobile PCs with Intel® 82430TX and 2 DIMMs or 3 SO-DIMMs  
82430TX or similar chipsets. There are three available options  
as shown in the selector guide  
Features  
• Mixed 2.5V and 3.3V operation  
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up  
to nine selectable frequencies. There are up to eight 3.3V  
SDRAM clocks and seven PCI clocks, running at one half the  
• Complete clock solution to meet requirements of  
Pentium®, Pentium® II, 6x86, or K6 motherboards  
— Four CPU clocks at 2.5V or 3.3V  
— Up to eight 3.3V SDRAM clocks  
CPU clock frequency. One of the PCI clocks is free-running.  
Additionally, the part outputs two 3.3V USB/IO clocks at 48  
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and  
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,  
USB, and IO clock frequencies are factory-EPROM program-  
mable for easy customization with fast turnaround times.  
— Seven 3.3V synchronous PCI clocks, one free  
running  
— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable  
by serial interface  
— One 2.5V IOAPIC clock at 14.318 MHz  
— Two 3.3V Ref. clocks at 14.318 MHz  
The CY2277A has power-down, CPU stop and PCI stop pins  
for power management control. The CPU stop and PCI stop  
are controlled by the MODE pin. They are multiplexed with  
SDRAM clock outputs, and are selected when the MODE pin  
is driven LOW. Additionally, these inputs are synchronized  
on-chip, enabling glitch-free transitions. When the  
CPU_STOP input is asserted, the CPU outputs are driven  
LOW. When the PCI_STOP input is asserted, the PCI outputs  
(except the free-running PCI clock) are driven LOW. Finally,  
when the PWR_DWN pin is asserted, the reference oscillator  
and PLLs are shut down, and all outputs are driven LOW.  
• Factory-EPROM programmable CPU, PCI, and USB/IO  
clock frequencies for custom configuration  
• Factory-EPROM programmable output drive and slew  
rate for EMI customization  
• MODE Enable pin for CPU_STOP and PCI_STOP  
• SMBus serial configuration interface  
• Available in space-saving 48-pin SSOP and TSSOP  
packages.  
The CY2277A outputs are designed for low EMI emission.  
Controlled rise and fall times, unique output driver circuits and  
factory-EPROM programmable output drive and slew-rate  
enable optimal configurations for EMI control.  
Functional Description  
The CY2277A is a Clock Synthesizer/Driver for Pentium,  
Pentium II, 6X86, and K6 portable PCs designed with the Intel®  
.
Pin Configuration  
Top View  
Logic Block Diagram  
IOAPIC (14.318 MHz)  
VDDQ2  
REF1  
REF0  
AV  
1
48  
47  
46  
45  
44  
43  
42  
41  
DD  
2
PWR_SEL  
REF [0–1]  
(14.318)  
XTALIN  
3
14.318  
MHz  
OSC.  
V
V
SS  
DDQ2  
XTALIN  
XTALOUT  
MODE  
4
IOAPIC  
XTALOUT  
5
PWR_DWN  
STOP  
LOGIC  
CPU  
PLL  
CPUCLK[0–3]  
6
V
SS  
V
CPUCLK0  
CPUCLK1  
7
DDQ3  
PCICLK_F  
PCICLK0  
8
VDDCPU  
9
V
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
DDCPU  
V
SS  
10  
11  
SDRAM[0–5]  
CPUCLK2  
CPUCLK3  
SEL  
EPROM  
PCICLK1  
PCICLK2  
12  
13  
V
SS  
SDRAM0  
SDRAM1  
MODE  
SDRAM6/CPU_STOP  
SDRAM7/PCI_STOP  
PCICLK3  
PCICLK4  
SYS  
PLL  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
V
V
DDQ3  
DDQ3  
PCICLK5  
V
SDRAM2  
SDRAM3  
/2  
SS  
SEL  
V
SS  
Delay  
SDATA  
SCLK  
30  
29  
28  
27  
26  
25  
SDRAM4  
SDRAM5  
PWR_DWN  
STOP  
LOGIC  
PCI[0–5]  
V
V
DDQ3  
DDQ3  
PCICLK_F  
USBCLK/IOCLK  
USBCLK/IOCLK  
SDRAM6/CPU_STOP  
SDRAM7/PCI_STOP  
SERIAL  
INTERFACE  
CONTROL  
LOGIC  
SCLK  
Divide and  
Mux Logic  
USBCLK/IOCLK[0:1]  
V
AV  
DD  
SS  
SDATA  
Rev 1.0, November 25, 2006  
2200 Laurelwood Road, Santa Clara, CA 95054  
Page 1 of 18  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com  
1234567...18

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