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CY2254ASC-1

更新时间: 2024-11-17 04:37:55
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SPECTRALINEAR 晶体驱动器外围集成电路光电二极管时钟
页数 文件大小 规格书
7页 111K
描述
Pentium㈢ Processor Compatible Clock Synthesizer/Driver

CY2254ASC-1 数据手册

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Y2254A  
CY2254A  
Pentium® Processor Compatible Clock Synthesizer/Driver  
• Freq. stability = 0.01% (max.)  
Features  
• Output duty cycle 45% min. to 55% max.  
• Multiple clock outputs to meet requirements of most  
Pentium® motherboards  
• Test mode support (1 option only)  
• 3.3V or 5.0V operation  
— Four pin-selectable CPU clocks @ 66.66 MHz, 60.0  
MHz, and50.0MHzforsupportof IntelTritonPCIset  
based PC  
• Internal pull-up resistors on S0, S1, and OE inputs  
Functional Description  
— 55.0 MHz pin-selectable CPU clock also available (2  
option only)  
The CY2254A is a Clock Synthesizer/Driver that provides the  
multiple clocks required for a Pentium-based PC. The  
CY2254A has low-skew outputs (< 250 ps between the CPU  
Clocks, < 250 ps between the PCI Clocks). In addition, the  
CY2254A CPU clock outputs have less than 200 ps  
cycle-to-cycle jitter. Finally, both the PCI and CPU clock  
outputs meet the 1 V/ns slew rate requirement of a Pentium  
processor-based system.  
— Six PCI clocks at 1/2 CPU Clock frequency  
— One I/O clock @ 24 MHz  
— OneKeyboardController clock@ 12MHz (1option)  
or one Universal Serial Bus clock @ 48 MHz  
(2 option)  
— Two Ref. clocks @ 14.318 MHz  
— Ref. 14.318 MHz Xtal oscillator input  
• CPU clock jitter < 200 ps cycle-to-cycle  
• Low skew outputs  
The CY2254A accepts a 14.318 MHz reference signal as its  
input. The CY2254A has 2 PLLs, one of which generates the  
CPU and PCI clocks, and the other generates the I/O and  
Keyboard Controller or USB clocks. The CY2254A runs off  
either a 3.3V or 5V supply.  
— < 250 ps between CPU clocks  
The CY2254A is available in two options. The 1 option  
supports the Intel Triton PCIset and provides a 12 MHz  
keyboard clock on pin 25. The 2 option provides a 48 MHz  
USB clock on pin 25 and supports the Cyrix® M1 processor.  
— < 250 ps between PCI clocks  
— < 500 ps between CPU and PCI clocks (2 option)  
— CPU clock leads PCI clock by +1 ns min. to +4 ns  
max. (1 option)  
Pin Configuration  
Logic Block Diagram  
REF0 (14.318 MHz)  
Top View  
REF1 (14.318 MHz)  
KBDCLK (12 MHz)  
SOIC  
SYS  
PLL  
y2  
y2  
V
REF0  
REF1  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
DD  
14.318  
MHz  
OSC.  
XTALIN  
XTALIN  
IOCLK (24 MHz)  
2
XTALOUT  
V
DD  
3
USBCLK (48 MHz)  
XTALOUT  
V
SS  
SEEBELOW  
IOCLK  
4
OE  
CPUCLK0  
CPUCLK1  
5
CPU  
PLL  
V
SS  
6
CPUCLK0  
CPUCLK1  
CPUCLK2  
CPUCLK3  
PCICLK2  
PCICLK3  
7
V
DD  
8
ROM  
CPUCLK2  
CPUCLK3  
V
DD  
9
PCICLK4  
PCICLK5  
10  
11  
12  
V
SS  
S0  
S1  
y2  
DELAY  
S1  
S0  
V
SS  
PCICLK1  
PCICLK0  
13  
14  
16  
15  
V
DD  
1 option only  
PCICLK0  
PCICLK1  
PCICLK2  
PCICLK3  
PIN 25  
OPTION  
KBDCLK  
12 MHz  
USBCLK  
48 MHz  
1  
2  
PCICLK4  
PCICLK5  
OE  
Rev 1.0, November 25, 2006  
2200 Laurelwood Road, Santa Clara, CA 95054  
Page 1 of 7  
www.SpectraLinear.com  
Tel:(408) 855-0555 Fax:(408) 855-0550  

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