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CY14B256L-SZ25XI PDF预览

CY14B256L-SZ25XI

更新时间: 2024-11-19 06:51:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
18页 642K
描述
256 Kbit (32K x 8) nvSRAM

CY14B256L-SZ25XI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.45最长访问时间:25 ns
JESD-30 代码:R-PDSO-G32JESD-609代码:e3
长度:20.726 mm内存密度:262144 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:32字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP32,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3/3.3 V认证状态:Not Qualified
座面最大高度:2.54 mm最大待机电流:0.003 A
子类别:SRAMs最大压摆率:0.07 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:7.5057 mm
Base Number Matches:1

CY14B256L-SZ25XI 数据手册

 浏览型号CY14B256L-SZ25XI的Datasheet PDF文件第2页浏览型号CY14B256L-SZ25XI的Datasheet PDF文件第3页浏览型号CY14B256L-SZ25XI的Datasheet PDF文件第4页浏览型号CY14B256L-SZ25XI的Datasheet PDF文件第5页浏览型号CY14B256L-SZ25XI的Datasheet PDF文件第6页浏览型号CY14B256L-SZ25XI的Datasheet PDF文件第7页 
CY14B256L  
256 Kbit (32K x 8) nvSRAM  
Features  
Functional Description  
25 ns, 35 ns, and 45 ns access times  
Pin compatible with STK14D88  
The Cypress CY14B256L is a fast static RAM with a nonvolatile  
element in each memory cell. The embedded nonvolatile  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM provides  
unlimited read and write cycles, while independent, nonvolatile  
data resides in the highly reliable QuantumTrap cell. Data  
transfers from the SRAM to the nonvolatile elements (the  
STORE operation) takes place automatically at power down. On  
power up, data is restored to the SRAM (the RECALL operation)  
from the nonvolatile memory. Both the STORE and RECALL  
operations are also available under software control. A hardware  
STORE is initiated with the HSB pin.  
Hands off automatic STORE on power down with only a small  
capacitor  
STORE to QuantumTrap™ nonvolatile elements is initiated by  
software, hardware, or AutoStore™ on power down  
RECALL to SRAM initiated by software or power up  
Unlimited READ, WRITE, and RECALL cycles  
200,000 STORE cycles to QuantumTrap  
20 year data retention at 55°C  
Single 3V +20%, –10% operation  
Commercial and industrial temperature  
32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages  
RoHS compliance  
Logic Block Diagram  
V
CC  
V
CAP  
Quantum Trap  
512 X 512  
POWER  
CONTROL  
A5  
STORE  
A6  
A7  
A8  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
512 X 512  
HSB  
A9  
A11  
A12  
A13  
A14  
SOFTWARE  
DETECT  
A13  
-
A0  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
DQ6  
DQ7  
A0  
A4  
A10  
A1  
A3  
A2  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-06422 Rev. *H  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised January 30, 2009  
[+] Feedback  

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