CY14B104LA
CY14B104NA
4-Mbit (512K × 8/256K × 16) nvSRAM
4-Mbit (512K
× 8/256K × 16) nvSRAM
■ Packages
Features
❐ 44-/54-pin thin small outline package (TSOP) Type II
❐ 48-ball fine-pitch ball grid array (FBGA)
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 512K × 8 (CY14B104LA) or 256K × 16
(CY14B104NA)
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
■ Hands off automatic STORE on power-down with only a small
capacitor
Functional Description
The Cypress CY14B104LA/CY14B104NA is a fast static RAM
(SRAM), with a non-volatile element in each memory cell. The
memory is organized as 512K bytes of 8 bits each or 256K words
of 16-bits each. The embedded non-volatile elements incor-
porate QuantumTrap technology, producing the world’s most
reliable non-volatile memory. The SRAM provides infinite read
and write cycles, while independent non-volatile data resides in
the highly reliable QuantumTrap cell. Data transfers from the
SRAM to the non-volatile elements (the STORE operation) takes
place automatically at power-down. On power-up, data is
restored to the SRAM (the RECALL operation) from the
non-volatile memory. Both the STORE and RECALL operations
are also available under software control.
■ STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20, –10 operation
■ Industrial temperature
For a complete list of related documentation, click here.
Logic Block Diagram [1, 2, 3]
VCC
VCAP
Quatrum Trap
2048 X 2048
A0
A1
A2
A3
A4
A5
A6
POWER
R
O
W
CONTROL
STORE
RECALL
STORE/RECALL
CONTROL
D
E
C
O
D
E
R
HSB
STATIC RAM
ARRAY
2048 X 2048
A7
A8
A17
SOFTWARE
DETECT
A14 - A2
A18
DQ0
DQ1
DQ2
DQ3
I
DQ4
DQ5
DQ6
N
P
U
T
B
U
F
F
E
R
S
DQ7
COLUMN I/O
DQ8
DQ9
DQ10
OE
COLUMN DEC
WE
DQ11
DQ12
DQ13
DQ14
CE
BLE
A11
A9 A10
A12 A13 A14 A15 A16
DQ15
BHE
Notes
1. Address A –A for × 8 configuration and Address A –A for × 16 configuration.
0
18
0
17
2. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.
0
7
0
15
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document Number: 001-49918 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 12, 2017