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CY14B101P PDF预览

CY14B101P

更新时间: 2024-02-07 09:58:16
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器时钟
页数 文件大小 规格书
33页 1516K
描述
1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock

CY14B101P 数据手册

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PRELIMINARY  
CY14B101P  
1 Mbit (128K x 8) Serial SPI nvSRAM  
with Real Time Clock  
Write Protection  
Features  
Hardware Protection using Write Protect (WP) Pin  
Software Protection using Write Disable Instruction  
Software Block Protection for 1/4, 1/2, or entire Array  
1 Mbit Nonvolatile SRAM  
Internally organized as 128K x 8  
STORE to QuantumTrap nonvolatile elements initiated  
automatically on power down (AutoStore) or by user using  
HSB pin (Hardware Store) or SPI instruction (Software Store)  
RECALL to SRAM initiated on power up (Power Up Recall)  
or by SPI Instruction (Software Recall)  
Automatic STORE on power down with a small capacitor  
Low Power Consumption  
Single 3V +20%, –10% operation  
Average VCC current of 10 mA at 40 MHz operation  
Industry Standard Configurations  
Commercial and industrial temperatures  
16-pin SOIC Package  
High Reliability  
RoHS compliant  
Infinite Read, Write, and RECALL cycles  
200,000 STORE cycles to QuantumTrap  
Data Retention: 20 Years  
Overview  
The Cypress CY14B101P combines a 1 Mbit nonvolatile static  
RAM with full featured real time clock in a monolithic integrated  
circuit with serial SPI interface. The memory is organized as  
128K words of 8 bits each. The embedded nonvolatile elements  
incorporate the QuantumTrap technology, creating the world’s  
most reliable nonvolatile memory. The SRAM provides infinite  
read and write cycles, while the QuantumTrap cells provide  
highly reliable nonvolatile storage of data. Data transfers from  
SRAM to the nonvolatile elements (STORE operation) takes  
place automatically at power down. On power up, data is  
restored to the SRAM from the nonvolatile memory (RECALL  
operation). The STORE and RECALL operations can also be  
initiated by the user.  
Real Time Clock  
Full featured Real Time Clock  
Watchdog timer  
Clock alarm with programmable interrupts  
Capacitor or battery backup for RTC  
Backup current of 300 nA  
High Speed Serial Peripheral Interface (SPI)  
40 MHz Clock rate - SRAM Memory access  
25 MHz Clock rate - RTC Memory access  
Supports SPI Modes 0 (0,0) and 3 (1,1)  
VCC  
VCAP  
Logic Block Diagram  
Quantum Trap  
128K X 8  
Power Control  
CS  
WP  
SCK  
Instruction decode  
Write protect  
Control logic  
STORE/RECALL  
Control  
STORE  
HSB  
SRAM ARRAY  
HOLD  
RECALL  
128K X 8  
Instruction  
register  
D0-D7  
A0-A16  
Xout  
Xin  
INT  
Address  
Decoder  
RTC  
MUX  
Data I/O register  
Status register  
SO  
SI  
Cypress Semiconductor Corporation  
Document #: 001-44109 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 02, 2009  
[+] Feedback  

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