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CXK77V3211Q-14 PDF预览

CXK77V3211Q-14

更新时间： 2024-11-07 22:08:51
品牌 Logo 应用领域
索尼 - SONY /
页数 文件大小 规格书
18页 570K
描述
32768-word by 32-bit High Speed Synchronous Static RAM

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CXK77V3211Q-14 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：QFP, QFP100(UNSPEC)
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：14 ns
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：32功能数量：1
端口数量：1端子数量：100
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX32
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100(UNSPEC)封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified座面最大高度：3.1 mm
子类别：SRAMs最大压摆率：0.26 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CXK77V3211Q-14 数据手册

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-12/14  
CXK77V3211Q  
32768-word by 32-bit High Speed Synchronous Static RAM  
For the availability of this product, please contact the sales office.  
Description  
100 pin QFP (Plastic)  
The CXK77V3211Q is a 32K × 32 high performance  
synchronous SRAM with a 2-bit burst counter and  
output register. All synchronous inputs pass through  
register controlled by a positive-edge-triggered  
single clock input (CLK). The synchronous inputs  
include all addresses, all data inputs, chip enable  
(CE), two additional chip enables for easy depth  
expansion (CE2, CE2), burst control inputs (ADSC,  
ADSP, ADV), four individual byte write enables  
(BW1, BW2, BW3, BW4), one byte write enable  
(BWE), and global write enable (SGW).  
Structure  
Silicon gate CMOS IC  
Asynchronous inputs include the output enable  
(OE) and power down control (ZZ). Two mode  
control pins (LBO, FT) define four different operation  
modes: Linear/Interleaved burst sequence and  
Flow-Thru/Pipelined operations.  
Features  
• Fast address access times and High frequency  
operation  
Flow-through  
Pipeline  
WRITE cycles can be from one to four bytes wide  
as controlled by BW1 through BW4 and BWE or  
SGW. The output register is included on-chip and  
controlled by clock, it can be activated by connecting  
FT to high for high speed pipeline operation.  
Symbol  
Access  
Cycle  
60MHz  
50MHz  
Access  
Cycle  
75MHz  
66MHz  
-12  
-14  
12ns  
14ns  
7ns  
8ns  
Burst operation can be initiated with either address  
status processor (ADSP) or address status  
controller (ADSC) input pins. Subsequent burst  
addresses can be internally generated as controlled  
by the burst advance pin (ADV). Burst order  
sequence can be controlled by connecting LBO to  
high for Interleaved burst order (i486/Pentium™) or  
by connecting LBO to low for Linear burst order.  
Address and write control are registered on-chip to  
simplify WRITE cycles. This allows self-timed  
WRITE cycles. Individual byte enables allow  
individual bytes to be written. WRITE pass through  
makes written data immediately available at the  
output register during READ cycle following a  
WRITE as controlled by OE.  
• 5V tolerant inputs except I/O pins  
• A FT pin for pipelined or flow-thru architecture  
• A LBO mode pin as burst control pin  
(i486/Pentium™ and Linear burst sequence)  
+10%  
• Single +3.3V  
power supply  
– 5%  
• Common data inputs and data outputs  
• All inputs and outputs are LVTTL compatible  
• Four Individual BYTE WRITE enables, GLOBAL  
WRITE and BYTE WRITE ENABLE  
• Three Chip Enables for simple depth expansion  
• One cycle output disable for both pipelined and  
flow-thru operation  
• Internal input registers for address, data and  
control signals  
• Self-timed WRITE cycle  
The CXK77V3211Q operates from a +3.3V power  
supply and all inputs and outputs are LVTTL  
compatible. The device is ideally suited for i486 and  
Pentium™ systems and those systems which  
benefit from a very wide data bus.  
• Write pass through capability  
• High 30pF output drive capability at rated access  
time  
• A ZZ pin for powerdown  
• 100-lead QFP package for high density, high  
speed operation  
i486/Pentium is a trademark of Intel Corp.  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E95721-PS  
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