Datasheet > 存储 > SRAM> CXK77P36E160GB-4E

CXK77P36E160GB-4E

更新时间： 2024-11-07 22:07:27

品牌	Logo	应用领域
索尼 - SONY		静态存储器
页数	文件大小	规格书
25页	259K
描述
16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

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SONYÒ

CXK77P36E160GB / CXK77P18E160GB 4/42/43/44

16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)

Preliminary

Description

The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read

operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

Two distinct R-L modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function

as conventional 16Mb R-L SRAMs, and pin 2B functions as a conventional SA address input. When M2 is “low”, these devices

function as Error-Correcting (EC) 8Mb R-L SRAMs, and pin 2B is ignored.

When Error-Correcting 8Mb R-L mode is selected, the SRAM is divided into two banks internally - a “primary” bank and a

“secondary” bank. During write operations, input data is ultimately written to both banks internally (through one stage of write

pipelining). During read operations, data is read from both banks internally, and each byte of primary bank data is individually

parity-checked. If the parity of a particular byte of primary data is correct (that is, “odd”), it is driven valid externally. If the

parity of a particular byte of primary data is incorrect (that is, “even”), it is discarded, and the corresponding byte of secondary

bank data is driven valid externally. Primary / secondary bank data selection is performed on each data byte independently.

Data read from the secondary bank is NOT parity-checked.

Data read from the write buffer is NOT parity-checked.

All address and control input signals except ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock).

During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V , the output impedance of all DQ pins can be precisely controlled.

Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single

3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

Features

•

4 Speed Bins

-4 (-4A) (-4B)

Cycle Time / Access Time

4.0ns / 3.9ns (3.8ns) (3.7ns)

4.2ns / 4.2ns (4.1ns) (4.0ns)

4.3ns / 4.5ns (4.4ns) (4.3ns)

4.4ns / 4.7ns

-42 (-42A) (-42B)

-43 (-43A) (-43B)

-44

•

Single 3.3V power supply (V ): 3.3V ± 5%

Dedicated output supply voltage (V

): 1.9V typical

DDQ

HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.85V typical

REF

Late Write (LW) write operations

Conventional 16Mb or Error-Correcting (EC) 8Mb mode of operation, selectable via dedicated mode pin (M2)

Full read/write coherency

Byte Write capability

One cycle deselect

Differential input clocks (K/K)

Programmable impedance output drivers

Sleep (power down) mode via dedicated mode pin (ZZ)

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1

1 / 25

March 2, 2001

12 3 4 5 6 7...25

中文翻译

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与CXK77P36E160GB-4E相关器件

型号	品牌	获取价格	描述	数据表
CXK77P36E160GB-4F	SONY	获取价格	Standard SRAM, 512KX36, 3.9ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36E160GB-4G	SONY	获取价格	暂无描述
CXK77P36E160GB-4H	SONY	获取价格	Standard SRAM, 512KX36, 3.9ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36L80AGB	ETC	获取价格	MEMORY-UHS Synch SRAMs 8Meg Ultra-High-Speed Synchronous SRAM (256K x 36) (25 pages 270K R
CXK77P36L80AGB-4	SONY	获取价格	Late-Write SRAM, 256KX36, 3.9ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-42A	SONY	获取价格	Late-Write SRAM, 256KX36, 4.1ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-42B	SONY	获取价格	Late-Write SRAM, 256KX36, 4ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
CXK77P36L80AGB-43	SONY	获取价格	Late-Write SRAM, 256KX36, 4.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-43A	SONY	获取价格	Late-Write SRAM, 256KX36, 4.4ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P36L80AGB-43B	SONY	获取价格	Late-Write SRAM, 256KX36, 4.3ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11

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