Datasheet > CXK77P18R160GB-4

CXK77P18R160GB-4

更新时间： 2024-11-11 14:48:43

品牌	Logo	应用领域
索尼 - SONY		静态存储器
页数	文件大小	规格书
22页	238K
描述
Late-Write SRAM, 1MX18, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

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中文翻译

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技术参数
数据手册

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CXK77P18R160GB-4 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA119,7X17,50	针数：	119
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
Is Samacsys：	N	Base Number Matches：	1

CXK77P18R160GB-4 数据手册

SONYÒ CXK77P36R160GB / CXK77P18R160GB

3/33/4

16Mb LW R-R HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

Preliminary

Description

The CXK77P36R160GB (organized as 524,288 words by 36 bits) and the CXK77P18R160GB (organized as 1,048,576 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R)

read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K

differential input clock.

During read operations, output data is driven valid from the rising edge of K, one full clock cycle after address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after address is registered.

Sleep (power down) capability is provided via the ZZ input signal.

Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external

control resistor RQ between ZQ and V , the impedance of all data output drivers can be precisely controlled.

333 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of

IEEE standard 1149.1 protocol.

Features

•

3 Speed Bins

Cycle Time / Access Time

3.0ns / 1.8ns

-3

-33

-4

3.3ns / 1.9ns

4.0ns / 2.0ns

•

Single 2.5V power supply (V ): 2.5V ± 5%

Dedicated output supply voltage (V

): 1.8V ± 0.1V

DDQ

HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.9V typical

REF

Late Write (LW) write protocol

Full read/write coherency

Byte Write capability

Differential input clocks (K/K)

Asynchronous output enable (G)

Sleep (power down) mode via dedicated mode pin (ZZ)

Programmable output driver impedance

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

16Mb LW R-R, rev 1.0

1 / 22

June 24, 2002

12 3 4 5 6 7...22

中文翻译

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与CXK77P18R160GB-4相关器件

型号	品牌	获取价格	描述	数据表
CXK77P36E160GB	SONY	获取价格	16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
CXK77P36E160GB-42AE	SONY	获取价格	16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
CXK77P36E160GB-42AF	SONY	获取价格	Standard SRAM, 512KX36, 4.1ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36E160GB-42AH	SONY	获取价格	Standard SRAM, 512KX36, 4.1ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36E160GB-42BE	SONY	获取价格	16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
CXK77P36E160GB-42E	SONY	获取价格	16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
CXK77P36E160GB-42F	SONY	获取价格	Standard SRAM, 512KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36E160GB-42G	SONY	获取价格	暂无描述
CXK77P36E160GB-43AE	SONY	获取价格	16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
CXK77P36E160GB-43AG	SONY	获取价格	Standard SRAM, 512KX36, 4.4ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

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