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CXK77P18R160GB-3 PDF预览

CXK77P18R160GB-3

更新时间: 2024-11-11 14:48:43
品牌 Logo 应用领域
索尼 - SONY 静态存储器内存集成电路
页数 文件大小 规格书
22页 238K
描述
Late-Write SRAM, 1MX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

CXK77P18R160GB-3 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.92
Is Samacsys:N最长访问时间:1.8 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:18874368 bit内存集成电路类型:LATE-WRITE SRAM
内存宽度:18功能数量:1
端子数量:119字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:1MX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:1.8,2.5 V
认证状态:Not Qualified座面最大高度:2.5 mm
最大待机电流:0.25 A最小待机电流:2.37 V
子类别:SRAMs最大压摆率:0.78 mA
最大供电电压 (Vsup):2.63 V最小供电电压 (Vsup):2.37 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:TIN LEAD端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:10宽度:14 mm
Base Number Matches:1

CXK77P18R160GB-3 数据手册

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SONYÒ CXK77P36R160GB / CXK77P18R160GB  
3/33/4  
16Mb LW R-R HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)  
Preliminary  
Description  
The CXK77P36R160GB (organized as 524,288 words by 36 bits) and the CXK77P18R160GB (organized as 1,048,576 words  
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input  
registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R)  
read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.  
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K  
differential input clock.  
During read operations, output data is driven valid from the rising edge of K, one full clock cycle after address is registered.  
During write operations, input data is registered on the rising edge of K, one full clock cycle after address is registered.  
Sleep (power down) capability is provided via the ZZ input signal.  
Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external  
control resistor RQ between ZQ and V , the impedance of all data output drivers can be precisely controlled.  
SS  
333 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of  
IEEE standard 1149.1 protocol.  
Features  
3 Speed Bins  
Cycle Time / Access Time  
3.0ns / 1.8ns  
-3  
-33  
-4  
3.3ns / 1.9ns  
4.0ns / 2.0ns  
Single 2.5V power supply (V ): 2.5V ± 5%  
DD  
Dedicated output supply voltage (V  
): 1.8V ± 0.1V  
DDQ  
HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.9V typical  
REF  
Register - Register (R-R) read protocol  
Late Write (LW) write protocol  
Full read/write coherency  
Byte Write capability  
Differential input clocks (K/K)  
Asynchronous output enable (G)  
Sleep (power down) mode via dedicated mode pin (ZZ)  
Programmable output driver impedance  
JTAG boundary scan (subset of IEEE standard 1149.1)  
119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package  
16Mb LW R-R, rev 1.0  
1 / 22  
June 24, 2002  

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