Datasheet > 存储 > SRAM> CXK77P18E160GB-4BE

CXK77P18E160GB-4BE

更新时间： 2024-11-10 22:07:27

品牌	Logo	应用领域
索尼 - SONY		静态存储器
页数	文件大小	规格书
25页	259K
描述
16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

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CXK77P18E160GB-4BE 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA119,7X17,50	针数：	119
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	3.7 ns	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
内存密度：	18874368 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	18	功能数量：	1
端子数量：	119	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：
组织：	1MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA119,7X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	1.9,3.3 V
认证状态：	Not Qualified	座面最大高度：	2.5 mm
最大待机电流：	0.25 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.75 mA
最大供电电压 (Vsup)：	3.47 V	最小供电电压 (Vsup)：	3.13 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	10	宽度：	14 mm
Base Number Matches：	1

CXK77P18E160GB-4BE 数据手册

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SONYÒ

CXK77P36E160GB / CXK77P18E160GB 4/42/43/44

16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)

Preliminary

Description

The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read

operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

Two distinct R-L modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function

as conventional 16Mb R-L SRAMs, and pin 2B functions as a conventional SA address input. When M2 is “low”, these devices

function as Error-Correcting (EC) 8Mb R-L SRAMs, and pin 2B is ignored.

When Error-Correcting 8Mb R-L mode is selected, the SRAM is divided into two banks internally - a “primary” bank and a

“secondary” bank. During write operations, input data is ultimately written to both banks internally (through one stage of write

pipelining). During read operations, data is read from both banks internally, and each byte of primary bank data is individually

parity-checked. If the parity of a particular byte of primary data is correct (that is, “odd”), it is driven valid externally. If the

parity of a particular byte of primary data is incorrect (that is, “even”), it is discarded, and the corresponding byte of secondary

bank data is driven valid externally. Primary / secondary bank data selection is performed on each data byte independently.

Data read from the secondary bank is NOT parity-checked.

Data read from the write buffer is NOT parity-checked.

All address and control input signals except ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock).

During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V , the output impedance of all DQ pins can be precisely controlled.

Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single

3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

Features

•

4 Speed Bins

-4 (-4A) (-4B)

Cycle Time / Access Time

4.0ns / 3.9ns (3.8ns) (3.7ns)

4.2ns / 4.2ns (4.1ns) (4.0ns)

4.3ns / 4.5ns (4.4ns) (4.3ns)

4.4ns / 4.7ns

-42 (-42A) (-42B)

-43 (-43A) (-43B)

-44

•

Single 3.3V power supply (V ): 3.3V ± 5%

Dedicated output supply voltage (V

): 1.9V typical

DDQ

HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.85V typical

REF

Late Write (LW) write operations

Conventional 16Mb or Error-Correcting (EC) 8Mb mode of operation, selectable via dedicated mode pin (M2)

Full read/write coherency

Byte Write capability

One cycle deselect

Differential input clocks (K/K)

Programmable impedance output drivers

Sleep (power down) mode via dedicated mode pin (ZZ)

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1

1 / 25

March 2, 2001

12 3 4 5 6 7...25

中文翻译

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与CXK77P18E160GB-4BE相关器件

型号	品牌	获取价格	描述	数据表
CXK77P18E160GB-4E	SONY	获取价格	16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
CXK77P18L80AGB	ETC	获取价格	MEMORY-UHS Synch SRAMs 8Meg Ultra-High-Speed Synchronous SRAM (512K x 18) (26 pages 224K R
CXK77P18L80AGB-4	SONY	获取价格	Late-Write SRAM, 512KX18, 3.9ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P18L80AGB-42	SONY	获取价格	Late-Write SRAM, 512KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P18L80AGB-42B	SONY	获取价格	Late-Write SRAM, 512KX18, 4ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
CXK77P18L80AGB-43	SONY	获取价格	Late-Write SRAM, 512KX18, 4.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P18L80AGB-43B	SONY	获取价格	Late-Write SRAM, 512KX18, 4.3ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P18L80AGB-44	SONY	获取价格	Late-Write SRAM, 512KX18, 4.7ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P18L80AGB-4A	SONY	获取价格	Late-Write SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77P18R160GB	ETC	获取价格	MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-Hi

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