Datasheet > 存储 > SRAM> CXK77K18R320GB-33

CXK77K18R320GB-33

更新时间： 2024-11-11 02:51:51

品牌	Logo	应用领域
索尼 - SONY		存储静态存储器
页数	文件大小	规格书
23页	198K
描述
32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)

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技术参数
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CXK77K18R320GB-33 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA119,7X17,50	针数：	119
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
Is Samacsys：	N	Base Number Matches：	1

CXK77K18R320GB-33 数据手册

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SONY

CXK77K18R320GB

3/33/4

32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)

Preliminary

Description

The CXK77K18R320GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 2,097,152 words

by 18 bits. This synchronous SRAMs integrates input registers, high speed RAM, output registers, and a one-deep write buffer

onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, pro-

viding a high-performance user interface.

All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K

differential input clock.

During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

Sleep (power down) capability is provided via the ZZ input signal.

Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external

control resistor RQ between ZQ and V_SS, the impedance of the output drivers can be precisely controlled.

333 MHz operation is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using a subset of

IEEE standard 1149.1 protocol.

Features

•

3 Speed Bins

Cycle Time / Access Time

3.0ns / 1.6ns

-3

-33

-4

3.3ns / 1.6ns

4.0ns / 2.0ns

• Single 1.8V power supply (V_DD): 1.8V ± 0.1V

Note: 2.5V V_DDis also supported. Please contact Sony Memory Marketing Department for further information.

• Dedicated output supply voltage (V_DDQ): 1.5V to 1.8V typical

• HSTL-compatible I/O interface with dedicated input reference voltage (V_REF): V_DDQ/2 typical

• Register - Register (R-R) read protocol

• Late Write (LW) write protocol

• Full read/write coherency

• Byte Write capability

• Differential input clocks (K/K)

• Asynchronous output enable (G)

• Sleep (power down) mode via dedicated mode pin (ZZ)

• Programmable output driver impedance

• JTAG boundary scan (subset of IEEE standard 1149.1)

• 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

32Mb LW R-R, rev 0.8

1 / 23

December 8, 2004

12 3 4 5 6 7...23

中文翻译

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与CXK77K18R320GB-33相关器件

型号	品牌	获取价格	描述	数据表
CXK77K18R320GB-4	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
CXK77K36R320GB	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)
CXK77K36R320GB-3	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)
CXK77K36R320GB-33	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)
CXK77K36R320GB-4	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)
CXK77L18162AGB	ETC	获取价格	MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-Hi
CXK77L18162GB	ETC	获取价格	MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed Synchronous SRAM (1M x 18) (23 pages 312K Re
CXK77L18162GB-25	SONY	获取价格	DDR SRAM, 1MX18, 1.8ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77L18162GB-3	SONY	获取价格	DDR SRAM, 1MX18, 1.9ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77L18R160GB	ETC	获取价格	MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 16Meg Ultra-Hi

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