Datasheet > CXK77B3640AGB-38

CXK77B3640AGB-38

更新时间： 2024-11-11 14:48:43

品牌	Logo	应用领域
索尼 - SONY		信息通信管理静态存储器内存集成电路
页数	文件大小	规格书
33页	284K
描述
Late-Write SRAM, 128KX36, 4.9ns, BICMOS, PBGA119

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CXK77B3640AGB-38 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	BGA, BGA119,7X17,50	Reach Compliance Code：	unknown
风险等级：	5.92	Is Samacsys：	N
最长访问时间：	4.9 ns	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B119	JESD-609代码：	e0
内存密度：	4718592 bit	内存集成电路类型：	LATE-WRITE SRAM
内存宽度：	36	端子数量：	119
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：		组织：	128KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA119,7X17,50
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	电源：	1.5,3.3 V
认证状态：	Not Qualified	最小待机电流：	3.14 V
子类别：	SRAMs	表面贴装：	YES
技术：	BICMOS	温度等级：	OTHER
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
Base Number Matches：	1

CXK77B3640AGB-38 数据手册

SONY

CXK77B3640AGB / CXK77B1840AGB

37/38/4/45

4Mb Late Write HSTL High Speed Synchronous SRAMs (128K x 36 or 256K x 18 Organization)

Preliminary

Description

The CXK77B3640A (organized as 131,072 words by 36 bits) and the CXK77B1840A (organized as 262,144 words by 18 bits)

are high speed BiCMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input registers,

high speed RAM, output registers/latches, and a one-deep write buffer onto a single monolithic IC. Four distinct read operation

protocols, Register - Register (R-R), Register - Latch (R-L), Register - Flow Thru (R-FT), and Dual Clock (DC), and one write

operation protocol, Late Write (LW), are supported, providing a flexible, high-performance user interface.

All address, data, and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the positive edge

of K clock. Read operation protocol is selectable through external mode pins M1 and M2.

Write operations are internally self-timed, eliminating the need for complex off-chip write pulse generation. In Register - Latch

and Register - Flow Thru modes, when SW (Global Write Enable) is driven active, the subsequent positive edge of K clock tri-

states the SRAM’s output drivers immediately, allowing Read-Write-Read operations to be initiated consecutively, with no dead

cycles between them.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V , the output impedance of all DQ pins can be precisely controlled.

Sleep (power down) mode control is provided through the asynchronous ZZ input. 270 MHz operation is obtained from a single

3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

Features

R-R Mode

/ t

R-L, R-FT Modes

/ t

**DC Mode**

/ t

• Fast Cycle / Access Time

KHKH KHQV

---------------------------------

------------------

3.45ns / 2.25ns

3.8ns / 2.25ns

5.0ns / 2.50ns

------------------

4.8ns / 4.6ns

4.8ns / 4.8ns

5.2ns / 5.2ns

6.0ns / 6.0ns

------------------

3.7ns / 4.9ns

3.8ns / 4.9ns

4.0ns / 5.2ns

4.5ns / 6.0ns

-37

-38

-4

-45

Note: Contact Sony Memory Marketing for availability of DC mode functionality in CXK77B1840A.

• Single 3.3V power supply (V ): 3.3V 5%

• Register - Register (R-R), Register - Latch (R-L), Register - Flow Thru (R-FT), or Dual Clock (DC) read operations

• Read operation protocol selectable via dedicated mode pins (M1, M2)

• Fully coherent, late write, self-timed write operations

• Byte Write capability

• Differential input clocks (K/K, C/C)

• Asynchronous output enable (G)

• Dedicated output supply voltage (V

): 1.5V typical, 2.0V maximum

DDQ

• HSTL-compatible I/O interface with dedicated input reference voltage (V

• Programmable impedance output drivers

): 0.75V typical

REF

• Sleep (power down) mode via dedicated mode pin (ZZ)

• JTAG boundary scan (subset of IEEE standard 1149.1)

• 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Plastic Ball Grid Array (PBGA) package

4Mb, Sync LW, HSTL, rev 1.5

1 / 33

July 23, 1998

12 3 4 5 6 7...33

中文翻译

下载PDF

与CXK77B3640AGB-38相关器件

型号	品牌	获取价格	描述	数据表
CXK77B3640AGB-4	SONY	获取价格	Late-Write SRAM, 128KX36, 5.2ns, BICMOS, PBGA119
CXK77B3640GB-45	ETC	获取价格	x36 Fast Synchronous SRAM
CXK77B3640GB-4A	ETC	获取价格	x36 Fast Synchronous SRAM
CXK77B3641GB-5	SONY	获取价格	Late-Write SRAM, 128KX36, 5.7ns, BICMOS, PBGA119, PLASTIC, BGA-119
CXK77B3641GB-6	SONY	获取价格	Late-Write SRAM, 128KX36, 6ns, BICMOS, PBGA119, PLASTIC, BGA-119
CXK77K18R320GB	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
CXK77K18R320GB-3	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
CXK77K18R320GB-33	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
CXK77K18R320GB-4	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18)
CXK77K36R320GB	SONY	获取价格	32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36)

与CXK77B3640AGB-38相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

7
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

8
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CXK77B3640AGB-38

CXK77B3640AGB-38 技术参数

CXK77B3640AGB-38 数据手册

与CXK77B3640AGB-38相关器件

与CXK77B3640AGB-38相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CXK77B3640AGB-38

CXK77B3640AGB-38 技术参数

CXK77B3640AGB-38 数据手册

与CXK77B3640AGB-38相关器件

与CXK77B3640AGB-38相关文章

您还可以找

您在本页遇到什么问题？