Single-Chip FaxEngine Product Family
Single-Chip FaxEngine (CXD9450)
and Integrated Analog Device (CX20415)
The Conexant™ Single-Chip FaxEngine product family consists of the Single-Chip
FaxEngine (CXD9450) that contains an embedded modem Digital Signal Processor
Features
(DSP), and a separate Integrated Analog (IA) device (20415).
Microprocessor and
Bus Interface
• MC24 Central Processing Unit
− Up to 10 MHz CPU clock speed
− Memory efficient input/output bit
manipulation
This device set, along with the supporting firmware and evaluation system,
comprises a complete facsimile machine—needing only power supply, scanner, and
printer mechanism components to complete the machine. A system-level block
diagram is shown in Figure 1.
− 24-bit internal address bus,
8-bit data bus
Integrated Controller
• External Bus
The integrated controller (SCC) provides the majority of the electronics necessary to
build a thermal or thermal transfer facsimile machine integrated into a one-chip
solution. The controller performs primary facsimile control/monitoring and
compression/decompression functions, and interfaces with fax machine
components such as a scanner, printer, motor, and operator control panel. The
MC24 embedded processor provides an external 16-MB direct memory access
capability. An integrated Pipeline ADC, combined with Conexant's Image
Processing Scheme, provides state of the art image processing performance on text
and gray scale images.
− Address, data, control, status,
and decoded chip select signals
support connection to external
ROM, SRAM, DRAM and
operator panel
− 24-bit external address bus
− 8-bit data bus
• Chip selects
− ROMCSn for ROM support
− CS0n for SRAM
− CS1n-CS5n for external I/O
− FCSn for FLASH memory
support
− LCDCS for LCD support
• DRAM Controller
− DRAM is refreshed in Sleep and
Stand-by modes
Embedded Modem DSP
The embedded modem DSP supports V.29 and V.27 ter facsimile transmission and
reception, in addition to all basic HDLC functions and T.30 requirements. The
modem allows all line connections and single or dual tone generation and detection.
Optional features such as V.17, voice compression/decompression for Digital
Telephone Answering Machine (DTAM), and duplex speakerphone are also
available.
− Up to 8 MB supported in two
blocks
Figure 1. Single-Chip FaxEngine System Level Block Diagram
− Organizations supported:
4 or 8-bit
− Single and page mode access
support
• Flash memory support
− NAND and NOR-type support
− Serial NAND support
− NOR-type memory up to 2 MB
• DMA Controller
Local
Handset
Single-Chip FaxEngine (CXD9450)
CCD or CIS
Scanner
Telephone
Line
DAA
Line IA
Thermal Printer or
Thermal Transfer
DSP
Secondary
Line IA
SCC
Speaker
Phone
Plain Paper
Inkjet Printer
(Optional)
Operator
Panel
− Six dedicated internal DMA
channels for scanner, thermal
printer, and T.4/T.6 access of
internal and/or external
memory.
− DMA Channel 2 can be
reprogrammed for external
access to plain paper inkjet
printing
24
NOR
FLASH
MB
ROM
DRAM
MB
SRAM
MB
8
2
MB
8
1
2
20
20
11
20
Control Bus
Data Bus
8
24
Address Bus
Data Sheet
Conexant
Doc. No. 100544C
September 8, 2000
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