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CXD5091AGG PDF预览

CXD5091AGG

更新时间: 2024-09-25 06:51:27
品牌 Logo 应用领域
索尼 - SONY 解码器
页数 文件大小 规格书
31页 346K
描述
Ultra low power Audio Decoder LSI

CXD5091AGG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA, BGA273,17X17,20针数:273
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PBGA-B273JESD-609代码:e1
长度:9 mm功能数量:1
端子数量:273最高工作温度:70 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA273,17X17,20
封装形状:SQUARE封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.2,2.8 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Other Consumer ICs最大供电电压 (Vsup):1.5 V
最小供电电压 (Vsup):1.35 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:10宽度:9 mm
Base Number Matches:1

CXD5091AGG 数据手册

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Ultra low power Audio Decoder LSI  
CXD5091AGG  
Description  
The CXD5091AGG is an audio decoder LSI that achieves super-low power consumption and supports many  
codecs. Useful interface such as NAND/NOR flash memory and Memory Stick is supported, and it comprises  
analog circuits such as audio D/A converter and SAR A/D converter. The CXD5091AGG is suitable for portable  
audio players and cellular phone audio backend.  
Features  
‹ CPU  
: ARM7TDMI  
: 320K bytes  
: 448K bytes  
: 45.1584MHz  
‹ RAM  
‹ ROM  
‹ Frequency  
‹ Peripherals  
Š Host interface  
: SRAM, NOR flash slave compatible  
Host processor can be connected.  
16/8-bit data bus, 4-chip select  
Š Bus interface  
: 16/8-bit data bus, 5-chip select  
An external acknowledge device is also supported.  
Š NAND flash interface  
: 4-symbol ECC, Reed-Solomon error correction  
4-chip select  
Š DMA controller  
: × 4ch  
Š Serial interface  
: × 2ch (1ch supports up to 3Mbps baud rate.)  
Š Clocked serial interface  
Š Memory Stick interface  
Š I2C bus interface  
Š Audio interface  
: × 2ch  
: MS-Pro × 1ch  
: × 1ch  
: × 1ch  
Either analog audio interface or I2S bus interface can be selected as transfer  
protocol.  
Š USB2.0  
: PHY included, Low/Full/High-speed device, 5 end points, Control/Interrupt/  
Bulk/Isochronous transfer  
Š 8-bit timer  
: × 8ch, internal clock/external event trigger  
: 16-bit × 1ch  
: 8-bit × 1ch  
Š Watchdog timer  
Š PWM pulse generator  
Š A/D converter  
: 10-bit × 8 analog inputs, SAR, 1Msps  
: 24-bit × 2  
Š Audio D/A converter  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license  
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating  
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
E06Z16  
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