CXD3204R

更新时间： 2024-02-29 20:19:35

品牌	Logo	应用领域
索尼 - SONY		电视
页数	文件大小	规格书
2页	41K
描述
IEEE1394 LSI for D-STB, D-VHS, and DTV

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CXD3204R 数据手册

CXD3204R

IEEE1394 LSI for D-STB, D-VHS, and DTV

Description

176-pin LQFP (Plastic)

The CXD3204R is an LSI integrating Link Layer and

Physical Layer conforming to the IEEE1394-1995 serial

bus standard on a single chip.

Link Layer provides MPEG2 transport stream

dedicated input interface and output interface, IEC958

audio stream I/O interface and output interface for D/A

converter as a data interface fo isochronous

communication. Also, a maximum 512 bytes of

asynchronous communication is possible.

Physical Layer provides two poarts for 1394 cable

interface, and supports transfer speed of

200/100Mbit/s. Also, this layer provides received packet

data regeneration repeat function, arbitration function

and bus initialization logic.

◆ Cable power reduction is detected with cable

power status

◆ Supports conﬁguration manager cable and power

class deﬁnition pin.

◆ Independent 2-port TpBias

This LSI utilizes Apple Computer’s Fire Wire

technology.

Feature Summary

Application

❒ Conforms to IEEE1394-1995 serial bus standard

❒ Supports 100Mbps/200Mbps

❒ Link layer

❒ Digital interface for D-STB, D-VHS and DTV

◆ Supports DVB transport streams

◆ Supports IEC958 audio stream

◆ Built-in PID ﬁlter function

Absolute Max. Ratings (T = 25^oC, V = 0V)

◆ 2-channel isochronous simultaneous

transmission/synchronous transmission and

reception

-0.5 ~ +4.6

❒ Supply voltage

❒ Input voltage

❒ Output voltage

❒ Operating temperature

❒ Storage temperature

-0.5 ~ V +0.5 V

◆ Supports DMA (2-channel) transfer using host

bus

-20 ~ +75

OPR

◆ Isochronous data inserted from asynchronous

data port

-55 ~ +150

STG

◆ Built-in cipher circuit conforming to DTCP format

Recommended Operating Conditions

◆ Large capacity FIFO

3.0 ~ 3.6

-20 ~ +75

❒ Supply voltage

❒ Operating temperature

¥ Isochronous Transmit/Receive FIFO:

960 x 32-bit x 2

OPR

¥ Asynchronous Transmit FIFO: 132 x 33-bit

¥ Asynchronous Receive FIFO: 133 x 33-bit

◆ CIP header automatic attachment/detection

❒ Physical layer

◆ Live wire detection function when port is

connected to operation node

◆ Automatic shutdown function against stopport for

powersaving

◆ Bus initialization and arbitration state machine

logic

◆ Re-synchronization for reception data for local

clock

◆ Link-On packet recognition

◆ DS link encode/decode

◆ 196.603MHz PLL

Revision 0.0 (5/22/99)

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