CXD3068Q

更新时间： 2024-01-18 18:55:55

品牌	Logo	应用领域
索尼 - SONY		消费电路商用集成电路数字信号处理器
页数	文件大小	规格书
134页	1214K
描述
CD Digital Signal Processor with Built-in Digital Servo

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CXD3068Q 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP, QFP80,.64SQ	针数：	80
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PQFP-G80	JESD-609代码：	e6
长度：	14 mm	功能数量：	1
端子数量：	80	最高工作温度：	75 °C
最低工作温度：	-20 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP80,.64SQ
封装形状：	SQUARE	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.85 mm
子类别：	Other Consumer ICs	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL EXTENDED
端子面层：	Tin/Bismuth (Sn/Bi)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	10	宽度：	14 mm
Base Number Matches：	1

CXD3068Q 数据手册

CXD3068Q

CD Digital Signal Processor with Built-in Digital Servo

Preliminary

Description

The CXD3068Q is a digital signal processor LSI for

CD players. This LSI incorporates a digital servo.

80 pin QFP (Plastic)

Features

• All digital signal processings during playback are

performed with a single chip

• Highly integrated mounting possible due to a built-

in RAM

Digital Signal Processor (DSP) Block

• Playback mode supporting CAV (Constant Angular

Velocity)

• Frame jitter free

Applications

• 0.5× to 4× continuous playback possible

• Allows relative rotational velocity readout

• Wide capture range playback mode

• Spindle rotational velocity following method

• Supports 1× to 4× playback variable pitch

playback

• Bit clock, which strobes the EFM signal, is

generated by the digital PLL.

• EFM data demodulation

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage

• Input voltage

V^DD

–0.5 to +4.6

(VSS – 0.5V to VDD + 0.5V)

–0.5 to +4.6

(VSS – 0.5V to VDD + 0.5V)

• Enhanced EFM frame sync signal protection

• Refined super strategy-based powerful error

correction

C1: double correction, C2: quadruple correction

Supported during 4× playback

• Noise reduction during track jumps

• Auto zero-cross mute

• Subcode demodulation and Sub-Q data error

detection

• Digital spindle servo

• Output voltage

V^O

• Storage temperature Tstg

Supply voltage difference

VSS – AVSS –0.3 to +0.3

DD – AVDD –0.3 to +0.3

–55 to +150

°C

•

Note) AVDD includes XVDD and AVSS includes XVSS.

Recommended Operating Conditions

2.7 to 3.6

• Supply voltage

• Operating temperature

Topr

VDD

• 16-bit traverse counter

• Asymmetry correction circuit

• CPU interface on serial bus

–20 to +75

°C

• Error correction monitor signal, etc. output from a

new CPU interface

• Servo auto sequencer

• Fine search performs track jumps with high

accuracy

• Digital audio interface output

• Digital level meter, peak meter

• Bilingual supported

Input/Output Capacitance

• Input pin

• Output pin

• I/O pin

C^O

CI/O

9 (Max.)

11 (Max.)

Note) Measurement conditions VDD = VI = 0V

fM = 1MHz

• VCO control mode

• CD TEXT data demodulation

• EFM playability reinforcement function

Digital Servo (DSSP) Block

• Microcomputer software-based flexible servo control

• Offset cancel function for servo error signal

• Auto gain control function for servo loop

• E:F balance, focus bias adjustment function

• Surf jump function supporting micro two-axis

• Tracking filter: 6 stages

Focus filter: 5 stages

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

PE00326-PS

12 3 4 5 6 7...134

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