CXD3059AR
CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost
Description
The CXD3059AR is a digital signal processor LSI for CD
players. This LSI incorporates a RF amplifier and digital servo,
high & bass boost, 1-bit DAC and analog low-pass filter.
120 pin LQFP (Plastic)
Features
• All digital signal processing during playback is performed with
a single chip
• Highly integrated mounting possible due to a built-in RF
amplifier
RF Block
• Supports 4× speed playback CD
• RF system equalizer
• Supports pickup built-in RF summing amplifier
• Gain level switch
• TE balance adjustment function
• Digital dynamics (compressor)
Volume increased by +5dB at low level
• 8× oversampling digital filter
Digital Signal Processor (DSP) Block
• Supports CAV (Constant Angular Velocity) playback
• Frame jitter free
(attenuation: 61dB, ripple within band: ±0.0075dB)
• Digital signal output possible after boost
• Serial data format selectable from (output)
20 bits/18 bits/16 bits (rearward truncation, MSB first)
• Digital attenuation: –∞, –60 to +6dB, 2048 steps (linear)
• Soft mute
• 0.5× to 4× speed continuous playback possible
• Allows relative rotational velocity readout
• Supports variable pitch playback
• The bit clock, which strobes the EFM signal, is generated by
the digital PLL.
• Digital de-emphasis
• High-cut filter
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
Supported during 4× speed playback
• Noise reduction during track jumps
• Auto zero-cross mute
Applications
CD players
Structure
Silicon gate CMOS IC
• Subcode demodulation and subcode-Q data error detection
• Digital spindle servo
Absolute Maximum Ratings (Ta = 25°C)
• 16-bit traverse counter
• Supply voltage 1
• Input voltage 1
• Output voltage 1
• Supply voltage 2
VDD, XVDD
VI1
VSS – 0.5 to +3.5
VSS – 0.3 to VDD + 0.3
VSS – 0.3 to VDD + 0.3
V
V
V
• Asymmetry correction circuit
• CPU interface on serial bus
VO1
• Error correction monitor signal, etc. output from CPU
interface
IOVDD0 to 2, AVDD0 to 5
IOVSS – 0.5 to +4.5
V
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• CD TEXT data demodulation
• Input voltage 2
• Output voltage 2
• Storage temperature
VI2
VO2
IOVSS – 0.3 to IOVDD + 0.3 V
IOVSS – 0.3 to IOVDD + 0.3 V
Tstg
–55 to +150
°C
• Supply voltage difference
IOVSS, AVSS, XVSS – VSS
–0.3 to +0.3
–0.3 to +0.3
V
V
XVDD – VDD
Digital Servo (DSSP) Block
IOVDD, AVDD, XVDD – VDD
–0.3 to +0.3
(IOVDD, AVDD, XVDD < 2.3V)
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
• Tracking filter: 6 stages,
V
Recommended Operating Conditions
• Supply voltage 1
• Supply voltage 2
VDD, XVDD
IOVDD0 to 2, AVDD0 to 5
2.5 ± 0.2
V
V
Focus filter: 5 stages
3.3 ± 0.3
• Operating temperature
Topr
Digital Filter, DAC and Analog Low-pass Filter Blocks
• Digital dynamic bass boost and high boost
Bass Boost: 4th-order IIR 24dB/Oct
+10dB/+14dB/+18dB/+22dB
–20 to +75
°C
I/O Pin Capacitance
• Input capacitance
CI
7 (Max.)
7 (Max.)
7 (Max.)
pF
pF
pF
High Boost: Second-order IIR 12dB/Oct
+4dB/+6dB/+8dB/+10dB
• Output capacitance CO
• I/O capacitance
CI/O
• Independent turnover frequency selection possible
Bass Boost: 125Hz/160Hz/200Hz
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
High Boost: 5kHz/7kHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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