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CXD3018Q PDF预览

CXD3018Q

更新时间: 2024-02-29 12:18:30
品牌 Logo 应用领域
索尼 - SONY 商用集成电路
页数 文件大小 规格书
134页 954K
描述
Consumer Circuit, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100

CXD3018Q 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP, QFP100,.9SQ针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PQFP-G100长度:20 mm
功能数量:1端子数量:100
最高工作温度:75 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.9SQ封装形状:RECTANGULAR
封装形式:FLATPACK电源:3.3 V
认证状态:Not Qualified座面最大高度:3.1 mm
子类别:Other Consumer ICs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL EXTENDED
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

CXD3018Q 数据手册

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CXD3018Q/R  
CD Digital Signal Processor with Built-in Digital Servo and DAC  
For the availability of this product, please contact the sales office.  
Description  
CXD3018Q  
CXD3018R  
The CXD3018Q/R is a digital signal processor LSI  
for CD players. This LSI incorporates a digital servo,  
digital filter, zero detection circuit, 1-bit DAC and  
analog low-pass filter on a single chip.  
100 pin QFP (Plastic)  
100 pin LQFP (Plastic)  
Features  
Digital Signal Processor (DSP) Block  
Playback mode which supports CAV (Constant  
Angular Velocity)  
Frame jitter free  
0.5× to 4× continuous playback possible  
Allows relative rotational velocity readout  
Supports spindle external control  
• Wide capture range playback mode  
Spindle rotational velocity following method  
Supports 1× speed to 4× speed playback  
16K RAM  
Applications  
CD players  
Structure  
Silicon gate CMOS IC  
Absolute Maximum Ratings  
Supply voltage VDD  
Input voltage  
EFM data demodulation  
–0.5 to +4.6  
–0.5 to +4.6  
(VSS – 0.5V to VDD + 0.5V)  
–0.5 to +4.6  
(VSS – 0.5V to VDD + 0.5V)  
V
V
Enhanced EFM frame sync signal protection  
SEC strategy-based error correction  
Subcode demodulation and Sub Q data error  
detection  
VI  
Output voltage VO  
V
Digital spindle servo  
Storage temperature  
Tstg  
Supply voltage difference  
VSS – AVSS  
VDD – AVDD –0.3 to +0.3  
Note) AVDD includes XVDD and AVSS includes XVSS.  
16-bit traverse counter  
–55 to +150  
–0.3 to +0.3  
°C  
Asymmetry compensation circuit  
CPU interface on serial bus  
Error correction monitor signal, etc. output from a  
new CPU interface  
V
V
Servo auto sequencer  
Digital audio interface outputs  
Digital level meter, peak meter  
CD TEXT data demodulation  
Recommended Operating Conditions  
Supply voltage VDD  
Operating temperature  
Topr  
2.7 to 3.6  
V
–20 to +75  
°C  
Digital Servo (DSSP) Block  
Microcomputer software-based flexible servo control  
Offset cancel function for servo error signal  
Auto gain control function for servo loop  
E:F balance, focus bias adjustment functions  
Surf jump function supporting micro two-axis  
Tracking filter: 6 stages, focus filter: 5 stages  
VDD [V]  
CD-DSP block  
Playback  
speed  
DAC block  
4×  
2×  
1×  
2.7 to 3.6  
2.7 to 3.6  
2.7 to 3.6  
2.7 to 3.6  
2.7 to 3.6  
Digital Filter, DAC and Analog Low-Pass Filter Blocks  
DBB (digital bass boost) function  
Double-speed playback supported  
Digital de-emphasis  
Digital attenuation  
Zero detection function  
I/O Capacitance  
Input pin  
CI  
9 (Max.)  
pF  
pF  
pF  
Output pin  
I/O pin  
CO  
CI/O  
11 (Max.)  
11 (Max.)  
Note) Measurement conditions VDD = VI = 0V  
fM = 1MHz  
8Fs oversampling digital filter  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E00438-PS  

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