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CV145NL PDF预览

CV145NL

更新时间: 2024-02-14 18:55:30
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
13页 116K
描述
Low Skew Clock Driver, PQCC72

CV145NL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:QCCN, LCC72,.39SQ,20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.9JESD-30 代码:S-PQCC-N72
JESD-609代码:e0逻辑集成电路类型:LOW SKEW CLOCK DRIVER
端子数量:72最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCN封装等效代码:LCC72,.39SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified子类别:Clock Drivers
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

CV145NL 数据手册

 浏览型号CV145NL的Datasheet PDF文件第2页浏览型号CV145NL的Datasheet PDF文件第3页浏览型号CV145NL的Datasheet PDF文件第4页浏览型号CV145NL的Datasheet PDF文件第5页浏览型号CV145NL的Datasheet PDF文件第6页浏览型号CV145NL的Datasheet PDF文件第7页 
1-TO-19 DIFFERENTIAL  
CLOCK BUFFER  
IDTCV145  
DESCRIPTION:  
FEATURES:  
TheCV145differentialbuffercomplieswithIntelDB1900G,andisdesigned  
to work in conjunction with the main clock of CK409, CK410/CK410M and  
CK410B etc., PLL is off in bypass mode and no clock detect.  
• Compliant with Intel DB1900G  
• DIF Clock Support  
19 differential clock output pairs @ 0.7 V  
150 ps skew performance across all outputs  
• OE pin Control of All Outputs  
• 3.3 V Operation  
• Gear Ratio supporting generation of clocks at a different  
frequency ratioed from the input.  
• Split outputs supporting options of 2 outputs @1:1 and  
remaining 17 pairs at an alternate gear  
• Pin level OE control of individual outputs  
• Multiple output frequency options up to 400Mhz as a gear ratio  
of input clocks of 100-400Mhz  
• Output is HCSL compatible  
• SMBus Programmable configurations  
• PLL Bypass Configurable  
• SMBus address configurable to allow multiple buffer control in  
a single control network  
• Programmable Bandwidth  
• Glitchfree transition between frequency states  
• Available in 72-pin VFQPFN package  
FUNCTIONALBLOCKDIAGRAM  
DIF_0  
OE_17_18#  
DIF_0#  
OE[16:5]#  
Output  
DIF_1  
OE_01234#  
Control  
DIF_1#  
DIF_2  
PD#  
DIF_2#  
DIF_3  
DIF_3#  
SCL  
SDA  
Output  
DIF_4  
SM Bus  
Controller  
Buffer  
DIF_4#  
DIF_5  
SA_2/PLL_BYPASS#  
DIF_5#  
DIF_6  
DIF_6#  
CLK_IN  
CLK_IN#  
DIF_18  
PLL  
DIF_18#  
HIGH_BW#  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
JUNE 2006  
1
© 2005 Integrated Device Technology, Inc.  
DSC-6753/14  

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