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CV141PVG8 PDF预览

CV141PVG8

更新时间: 2024-09-21 15:45:47
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 81K
描述
PLL Based Clock Driver, 141 Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, GREEN, SSOP-48

CV141PVG8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:GREEN, SSOP-48针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N系列:141
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:15.875 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:48实输出次数:8
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:0.25 ns传播延迟(tpd):4.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:2.79 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.49 mmBase Number Matches:1

CV141PVG8 数据手册

 浏览型号CV141PVG8的Datasheet PDF文件第2页浏览型号CV141PVG8的Datasheet PDF文件第3页浏览型号CV141PVG8的Datasheet PDF文件第4页浏览型号CV141PVG8的Datasheet PDF文件第5页浏览型号CV141PVG8的Datasheet PDF文件第6页浏览型号CV141PVG8的Datasheet PDF文件第7页 
1-TO-8 DIFFERENTIAL  
CLOCK BUFFER  
IDTCV141  
DESCRIPTION:  
FEATURES:  
TheCV141differentialbufferiscompliantwithIntelDB800specifications. It  
isintendedtodistributetheSRC(serialreferenceclock)asacompanionchip  
tothe mainclockofthe CK409,CK410/CK410M,CK410B,etc. PLLis offin  
bypass modeandhas noclockdetect.  
• Compliant with Intel DB800 spec  
• Eight differential clock pairs at 0.7V  
• 50ps skew  
• 50ps cycle-to-cycle jitter  
• Programmable Bandwidth  
• PLL bypass configurable  
Divide by 2 programmable  
Available in SSOP and TSSOP packages  
FUNCTIONALBLOCKDIAGRAM  
OE_INV  
DIF_0  
(1)OE[7:0]  
DIF_0#  
Output  
(1)SRC_STOP  
(1)PWRDWN  
Control  
DIF_1  
DIF_1#  
DIF_2  
DIF_2#  
SCL  
SDA  
SM Bus  
Controller  
DIF_3  
Output  
Buffer  
DIF_3#  
DIF_4  
SRC_DIV2#  
DIF_4#  
DIF_5  
PLL/BYPASS#  
DIF_5#  
SRC_IN  
DIF_6  
SRC_IN#  
DIF_6#  
DIV  
DIF_7  
HIGH_BW#  
PLL  
DIF_7#  
LOCK  
NOTE:  
1. See OE_INV table for active HIGH or active LOW.  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
OCTOBER 2005  
1
© 2005 Integrated Device Technology, Inc.  
DSC 6738/19  

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