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CSPPT32-470F

更新时间： 2024-01-27 13:20:15

品牌	Logo	应用领域
CALMIRCO		/
页数	文件大小	规格书
4页	61K
描述
CHIP SCALE PARALLEL TERMINATION ARRAY

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数据手册

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CSPPT32-470F 数据手册

CALIFORNIA MICRO DEVICES

CSPPT

Chip Scale ParallelTermination Array

Features

Applications

• 8,16 or 32 integrated high frequency

bussed terminations

• Parallel resistive bus termination

• Bussed resistor array

• Ultra small footprint Chip Scale Package

• Ceramic substrate

• 0.35mm Eutectic Solder Bumps, 0.65mm pitch

Product Description

The CSPPT is a high performance Integrated Passive

Device (IPD) which provides parallel terminations

suitable for use in high speed bus applications. Eight (8),

sixteen (16), or thirty-two (32) parallel termination

versions are provided. These resistors provide excellent

high frequency performance in excess of 3GHz and are

manufactured to an absolute tolerance as low as 1ꢀ.

The Chip Scale Package provides an ultra small

footprint for this IPD and provides minimal parasitics

compared to conventional packaging. Typical bump

inductance is less than 25pH. The large solder bumps

and ceramic substrate allow for standard attachment to

laminate printed circuit boards without the use of

underfill.

SCHEMATIC DIAGRAMS

CSPPT08

CSPPT16

CSPPT32

C1290700

11/10/2000 215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

12 3 4

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