Datasheet > 电阻器 > 阵列/网络电阻器> CSPPT08-500F

CSPPT08-500F

更新时间： 2024-01-07 23:24:42

品牌	Logo	应用领域
CALMIRCO		/
页数	文件大小	规格书
4页	61K
描述
CHIP SCALE PARALLEL TERMINATION ARRAY

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技术参数
数据手册

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CSPPT08-500F 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
风险等级：	5.84	Is Samacsys：	N
元件功耗：	0.1 W	第一元件电阻：	50 Ω
安装特点：	SURFACE MOUNT	网络类型：	BUSSED
元件数量：	8	功能数量：	1
端子数量：	10	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装形状：	RECTANGULAR PACKAGE
包装方法：	TR, 7 INCH	电阻器类型：	ARRAY/NETWORK RESISTOR
子类别：	Array/Network Resistors	表面贴装：	YES
温度系数：	150 ppm/ °C	端子形状：	BALL
容差：	5%	Base Number Matches：	1

CSPPT08-500F 数据手册

CALIFORNIA MICRO DEVICES

CSPPT

Chip Scale ParallelTermination Array

Features

Applications

• 8,16 or 32 integrated high frequency

bussed terminations

• Parallel resistive bus termination

• Bussed resistor array

• Ultra small footprint Chip Scale Package

• Ceramic substrate

• 0.35mm Eutectic Solder Bumps, 0.65mm pitch

Product Description

The CSPPT is a high performance Integrated Passive

Device (IPD) which provides parallel terminations

suitable for use in high speed bus applications. Eight (8),

sixteen (16), or thirty-two (32) parallel termination

versions are provided. These resistors provide excellent

high frequency performance in excess of 3GHz and are

manufactured to an absolute tolerance as low as 1ꢀ.

The Chip Scale Package provides an ultra small

footprint for this IPD and provides minimal parasitics

compared to conventional packaging. Typical bump

inductance is less than 25pH. The large solder bumps

and ceramic substrate allow for standard attachment to

laminate printed circuit boards without the use of

underfill.

SCHEMATIC DIAGRAMS

CSPPT08

CSPPT16

CSPPT32

C1290700

11/10/2000 215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

12 3 4

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