CS8411
CS8412
Digital Audio Interface Receiver
Features
Description
The CS8411/12 are monolithic CMOS devices which re-
ceive and decode audio data according to the AES/EBU,
IEC958, S/PDIF, & EIAJ CP-340 interface standards.
The CS8411/12 receive data from a transmission line,
recover the clock and synchronization signals, and de-
multiplex the audio and digital data. Differential or single
ended inputs can be decoded.
l Monolithic CMOS Receiver
l Low-Jitter, On-Chip Clock Recovery
256x Fs Output Clock Provided
l Supports: AES/EBU, IEC958, S/PDIF, &
EIAJ CP-340 Professional and Consumer
Formats
l Extensive Error Reporting
The CS8411 has a configurable internal buffer memory,
read via a parallel port, which may be used to buffer
channel status, auxiliary data, and/or user data.
- Repeat Last Sample on Error Option
l On-Chip RS422 Line Receiver
l Configurable Buffer Memory (CS8411)
The CS8412 de-multiplexes the channel, user, and va-
lidity data directly to serial output pins with dedicated
output pins for the most important channel status bits.
ORDERING INFORMATION
See page 32.
I
VD+
7
DGND
8
VA+
22
FILT
20
AGND
21
MCK
CS8411
19
26
12
11
SDATA
SCK
Audio
Serial Port
9
FSYNC
RXP
RXN
13
RS422
Receiver
De-MUX
A4/FCK
A3-A0
Clock and Data Recovery
10
4
8
Configurable
Buffer
Memory
D7-D0
IEnable and Status
25 14
ERF INT
24
23
CS
RD/WR
VD+
DGND
VA+
22
FILT
20
AGND
21
MCK
19
M3 M2
17 18
M1 M0
24 23
CS8412
7
8
26
12
11
SDATA
SCK
Audio
9
Serial Port
Registers
RXP
RXN
FSYNC
RS422
Receiver
De-MUX
Clock and Data Recovery
MUX
10
1
14
C
U
28
MUX
13
VERF
16
6
5
4
3
2
27
C0/ Ca/ Cb/ Cc/ Cd/ Ce/
E0 E1 E2 F0 F1 F2
25
15
CS12/
FCK
SEL
ERF CBL
Cirrus Logic, Inc.
Copyright Cirrus Logic, Inc. 1998
(All Rights Reserved)
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
OCT ‘98
DS61F1
1