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CS8130 PDF预览

CS8130

更新时间: 2024-01-18 05:08:29
品牌 Logo 应用领域
凌云 - CIRRUS 商用集成电路光电二极管
页数 文件大小 规格书
4页 28K
描述
MULTI STANDARD INFRARED TRANSCEIVER

CS8130 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:5 X 7 MM, SSOP-20Reach Compliance Code:unknown
风险等级:5.88商用集成电路类型:TRANSMITTER/RECEIVER IC
JESD-30 代码:R-PDSO-G20功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.7 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED传输媒体:INFRARED
Base Number Matches:1

CS8130 数据手册

 浏览型号CS8130的Datasheet PDF文件第2页浏览型号CS8130的Datasheet PDF文件第3页浏览型号CS8130的Datasheet PDF文件第4页 
11/6/97  
CS8130 Revision G Addendum  
Multi-Standard Infrared Transceiver (DS134PP2, JUN ‘97)  
The following items represent permanent changes to the specification of the CS8130 IR transceiver.  
1) The Silicon Revision Register (Register 28) reads 0010, indicating rev G silicon.  
2) The default receive sensitivity setting is changed to 00011 (Register 6 resets to 0011).  
3) Oscillator low power mode is now the default condition after reset (Register 21 resets to 0100).  
4) The BLKR bit (Register 4, bit D2) blocks the RXD output data during those periods when the transmit  
LEDs are on. This prevents the UART/system reading the transmitted data. The re-enable signal for  
the receiver is delayed by 8 µs from when the LEDs are turned off. Set to 1 to block RXD data, set to  
0 to allow RXD data through during transmission. This bit goes to 0 upon RESET.  
5) An additional control bit was added which causes the CS8130 receiver to ignore the falling edge of the  
IR pulse. This bit is called ENPOS, and it is bit D2 of Register #7. ENPOS is normally 1, which causes  
the falling edge to be ignored. This results in greater range in IrDA and high-frequency ASK (Sharp  
500 kHz) modes. ENPOS should be set to 0 for low-frequency amplitude modulated modes.  
6) For IrDA/HP-SIR pulse width modes, two additional control bits have been added:  
a. The THIN bit (Register 7, bit D1) allows the minimum acceptable pulse width to be reduced from  
1 µs to 0.5 µs when set to 1. This bit has effect only when the receiver is programmed to mode 1a  
(fixed 1.6 µs pulses only) or 1c (receive 1.6 µs to 3/16 of a bit cell pulses). This bit resets to 0.  
b. The WIDE bit (Register 1, Bit D2) expands the maximum allowable pulse width to 9/16 of a bit  
cell when set to 1. This bit has effect only when the receiver is set to mode 1a (fixed 1.6 µs pulses  
only).  
For normal IrDA operation, it is recommended that THIN be set to 0 and WIDE be set to 1. Under these  
conditions, the qualification boundaries for receiver mode 1c (receive 1.6 µs to 3/16 of a bit cell pulses)  
are identical to the qualification boundaries for receiver mode 1a (fixed 1.6 µs pulses only). This bit  
resets to 1.  
7) A TV remote receive mode hesitate bit has been added (Register 1, Bit D3). When this bit is set to 0,  
the RXD pin will remain high until the first valid IR signal is detected. At that time, the RXD pin will  
output serial data at the specified baud rate until the receiver is disabled (Register 0, bit D1). If this bit  
is set to 1, the RXD pin will immediately and continuously output data. This bit resets to 0.  
8) The ASK transmit carrier frequency formula has changed:  
MD=(3.6864E6/FR)-2 , where MD is the Modulator Divider Value and FR is the desired modulation  
frequency (Registers 10 & 11). The RESET default value for MD is now 5, yielding a default carrier  
Cirrus Logic, Inc.  
Copyright Cirrus Logic, Inc. 1997  
P.O. Box 17847, Austin, Texas 78760  
(512) 445 7222 FAX: (512) 445 7581  
http://www.cirrus.com  
DS134PP2-B  
NOV ‘97  
1
(All Rights Reserved)  

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