CS61581

更新时间： 2024-11-05 22:40:19

品牌	Logo	应用领域
凌云 - CIRRUS		/
页数	文件大小	规格书
37页	812K
描述
T1/E1 Universal Line Interface

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CS61581 数据手册

CS61581

T1/E1 Universal Line Interface

– FCC Rules and Regulations: Part 68 and Part

Features

l Provides T1 and E1, Long Haul and Short

Haul Line Interface

l Provides a QRSS Test Signal and Error

Detector

– AT&T Publication 62411

– ETSI ETS 300 011, 300 233, TBR 12/13

– TR-NET-00499

Description

l Impedance Matching Line Driver Using a

Single Transformer

l Greater than 14 dB of Transmit Return Loss

Without Using External Resistors

l No Crystal Needed for Jitter Attenuation

l Meets AT&T 62411 and TBR 12/13 Jitter

Tolerance and Attenuation Requirements

l Meets ANSI T1.231B and ITU-T G.775

Requirements for LOS and AIS

l Meets the BS6450 Transmitter Short-Circuit

Requirements for E1 Applications

l Compliant with:

– ITU-T Recommendations: G.703, G.732,

G.775 and I.431

The CS61581 is a primary rate line interface unit capa-

ble of operation in both short haul (intraoffice) and long

haul applications. The CS61581 combines the com-

plete analog transmit and receive circuitry for a single,

full-duplex interface at T1 and E1 rates. The device is

pin and function compatible with the Level One LXT310

and LXT318 (the latter in the host mode only). The de-

vice can also replace LXT359 and LXT360. Enhanced

functionality is available through an extended register

set allowing short haul operation, custom pulse shape

generation, QRSS pattern generation, detection and er-

ror counting, and generation and detection of loop up

and loop down codes. The CS61581 features Crystal^®

low-power impedance-matched line drivers and crystal-

less jitter attenuation.

ORDERING INFORMATION

– American National Standards (ANSI): T1.102,

T1.105, T1.403, T1.408, and T1.231

CS61581-IL

CS61581-IP

28-pin PLCC

28-pin PDIP

TCLK

PULSE

TRANSMIT

TIMING &

CONTROL

JITTER

ATTEN

SHAPING

CIRCUITRY

ROM / RAM

TTIP

TDATA/TPOS

UBS/TNEG

LINE DRIVERS

SERIAL

TRING

CLKE/TAOS

CS/RLOOP

SCLK/LLOOP

SDI/LBO1

JASEL

TAOS Enable

LBO Select

PORT

LOCAL

REMOTE

LOOPBACK

REGISTERS & CONTROL LOGIC

SDO/LBO2

LOOPBACK

(DIGITAL)

LOS/

NLOOP

Clear

LLOOP

Enable

LOCAL

LOOPBACK

(ANALOG)

SH/LH

EQUALIZER

CONTROL

LATN

RCLK

RDATA/RPOS

BPV/RNEG

TIMING

& DATA

RECOVERY

JITTER

ATTEN

SLICERS

& PEAK

DETECT

NOISE &

RTIP

MAGNITUDE

EQUALIZER

CROSSTALK

FILTERS

AGC

RRING

RECEIVE

CLOCK

GENERATOR

INBAND

NLOOP

& LOS

INT/NLOOP

LOS

MCLK

PROCESSOR

TV+

XTALIN

XTALOUT

MODE RV+ RGND TGND

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Preliminary Product Information

DS211PP8

AUG ‘05

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

APR ‘00

DS211F1

12 3 4 5 6 7...37

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与CS61581相关器件

型号	品牌	获取价格	描述	数据表
CS61581-IL	CIRRUS	获取价格	T1/E1 Universal Line Interface
CS61581-ILZ	CIRRUS	获取价格	暂无描述
CS61581-IP	ETC	获取价格	PCM Transceiver
CS61582	CIRRUS	获取价格	DUAL T1/E1 LINE INTERFACE
CS61582-IQ5	CIRRUS	获取价格	DUAL T1/E1 LINE INTERFACE
CS61583	CIRRUS	获取价格	DUAL T1/E1 LINE INTERFACE
CS61583-IL5	CIRRUS	获取价格	DUAL T1/E1 LINE INTERFACE
CS61583-IQ5	CIRRUS	获取价格	DUAL T1/E1 LINE INTERFACE
CS61584	ETC	获取价格	Dual T1/E1 Line Interface
CS61584A	CIRRUS	获取价格	DUAL T1/E1 LINE INTERFACE

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