Datasheet > CS61318-IP

CS61318-IP

更新时间： 2024-10-31 21:54:23

品牌	Logo	应用领域
凌云 - CIRRUS		/
页数	文件大小	规格书
28页	422K
描述
E1 LINE INTERFACE UNIT

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CS61318-IP 数据手册

CS61318

E1 Line Interface Unit

Features

Description

■ E1 Line Interface Unit

The CS61318 is an E1 primary rate line interface unit.

This device combines the complete analog transmit and

receive circuitry for a single, full-duplex interface E1

rates. The device provides jitter attenuation compliant to

CTR12/TBR13 without requiring an external crystal. Al-

■ No Crystal Needed for Jitter Attenuation

■ Meets CTR-12/TBR-12 Jitter Tolerance and Attenu-

ation Requirements

■ Meets ITU-T G.775 Requirements for LOS and AIS so, the CS61318 is pin and function compatible with the

Level One LXT318.

■ Meets the BS6450 Transmitter Short-Circuit

Requirements for E1 Applications

In addition to a basic hardware control mode, a host

mode is available that gives the user an enhanced func-

tionality via a serial microprocessor interface. The

extended features include custom pulse shape genera-

tion, AIS and LOS monitoring functions, signal strength

monitoring, and generation and detection of loop up and

loop down codes.

■ AWG for User Programmable Pulse Shapes

■ Line Quality Monitoring Function

■ TX Driver High Impedance / Low Power Control

■ AIS and LOS Monitoring

■ Generation and Detection of Loop Up / Loop Down

Signaling

■ Selectable HDB3 Encoding/Decoding

■ Selectable Unipolar or Bipolar I/O

■ Compliant with:

— ITU-T Recommendations: G.703, G.732, G.775, I.431

— ETSI ETS 300 011, 300 233, CTR 12, TBR 13

— TR-NET-00499

ORDERING INFORMATION

CS61318-IL

CS61318-IP

28-pin PLCC

28-pin PDIP

TCLK

PULSE

TRANSMIT

TIMING &

CONTROL

JITTER

ATTEN

SHAPING

CIRCUITRY

ROM / RAM

TTIP

TDATA/TPOS

UBS/TNEG

LINE DRIVERS

TRING

CLKE/TAOS

CS/RLOOP

SCLK/LLOOP

SDI/LBO1

JASEL

SERIAL

PORT

TAOS Enable

LOCAL

REMOTE

LOOPBACK

REGISTERS & CONTROL LOGIC

SDO/LBO2

LOOPBACK

(DIGITAL)

LOS/

NLOOP

Clear

LLOOP

Enable

LOCAL

LOOPBACK

(ANALOG)

EQUALIZER

CONTROL

LATN

RCLK

RDATA/RPOS

BPV/RNEG

TIMING

JITTER

ATTEN

& DATA

RECOVERY

SLICERS

& PEAK

DETECT

NOISE &

CROSSTALK

FILTERS

MAGNITUDE

EQUALIZER

RTIP

AGC

RRING

RECEIVE

CLOCK

GENERATOR

INBAND

NLOOP

& LOS

INT/NLOOP

LOS

MCLK

PROCESSOR

TV+

XTALIN

XTALOUT

MODE RV+ RGND TGND

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Preliminary Product Information

DS441PP2

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

AUG ‘99

12 3 4 5 6 7...28

中文翻译

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