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CS61310-IL

更新时间: 2024-11-17 22:28:47
品牌 Logo 应用领域
凌云 - CIRRUS 电信集成电路PC
页数 文件大小 规格书
30页 494K
描述
T1 INE INTERFACE UNIT

CS61310-IL 数据手册

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CS61310  
T1 Line Interface Unit  
Features  
Description  
The CS61310 is a T1 primary rate line interface unit. It  
combines the complete analog transmit-and-receive cir-  
cuitry for a single, full-duplex interface at T1 rates. The  
device is pin- and function-compatible with the Level  
One LXT310.  
Provides T1 line interface  
No crystal needed for jitter attenuation  
Greater than 14 dB of transmit return loss  
Meets AT&T 62411 jitter tolerance and  
attenuation requirements  
Meets ANSI T1.231B requirements for LOS and  
AIS  
AWG for user programmable pulse shapes  
TX driver high impedance / low power control  
Generation and detection of loop up / loop down  
signaling  
Enhanced functionality is available through an extended  
register set, allowing custom pulse shape generation as  
well as generation and detection of loop up and loop  
down codes. The CS61310 features crystal-less jitter  
attenuation.  
Selectable unipolar or bipolar I/O  
Compliant with:  
— American National Standards (ANSI): T1.102, T1.105,  
T1.403, T1.408, and T1.231  
— FCC Rules and Regulations: Part 68 and Part 15  
— AT&T Publication 62411  
— TR-NET-00499  
ORDERING INFORMATION  
CS61310-IL  
28-pin PLCC  
E
N
2
TCLK  
PULSE  
13  
C
O
D
E
R
TRANSMIT  
TIMING &  
CONTROL  
SHAPING  
CIRCUITRY  
ROM / RAM  
3
4
JITTER  
ATTEN  
TTIP  
TDATA/TPOS  
UBS/TNEG  
LINE DRIVERS  
16  
TRING  
28  
26  
27  
24  
25  
CLKE/TAOS  
CS/RLOOP  
SCLK/LLOOP  
SDI/LBO1  
11  
JASEL  
SERIAL  
PORT  
TAOS Enable  
LBO Select  
LOCAL  
REMOTE  
LOOPBACK  
(DIGITAL)  
REGISTERS & CONTROL LOGIC  
SDO/LBO2  
LOOPBACK  
LOS/  
NLOOP  
LLOOP  
Enable  
LOCAL  
Clear  
LOOPBACK  
(ANALOG)  
D
E
C
O
D
E
R
EQUALIZER  
CONTROL  
18  
8
7
6
LATN  
RCLK  
RDATA/RPOS  
BPV/RNEG  
TIMING  
JITTER  
ATTEN  
& DATA  
RECOVERY  
19  
20  
SLICERS  
& PEAK  
DETECT  
NOISE &  
CROSSTALK  
FILTERS  
RTIP  
MAGNITUDE  
EQUALIZER  
AGC  
RRING  
RECEIVE  
CLOCK  
GENERATOR  
INBAND  
NLOOP  
& LOS  
23  
12  
1
INT/NLOOP  
LOS  
MCLK  
PROCESSOR  
9
10  
5
21  
22  
14  
15  
TV+  
XTALIN  
XTALOUT  
MODE RV+ RGND TGND  
This document contains advanced information for a new product.  
Cirrus Logic reserves the right to modify this product without notice.  
Final Product Information  
Cirrus Logic, Inc.  
http://www.cirrus.com  
DS440F1  
FEB ‘03  
Copyright Cirrus Logic, Inc. 2003  
(All Rights Reserved)  
1

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