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CS5581_08 PDF预览

CS5581_08

更新时间: 2022-12-28 02:28:13
品牌 Logo 应用领域
凌云 - CIRRUS /
页数 文件大小 规格书
32页 505K
描述
±2.5 V / 5 V, 200 kSps, 16-bit, High-throughput ΔΣ ADC

CS5581_08 数据手册

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3/25/08  
15:11  
CS5581  
±2.5 V / 5 V, 200 kSps, 16-bit, High-throughput ∆Σ ADC  
Features & Description  
General Description  
The CS5581 is a single-channel, 16-bit analog-to-digital  
converter capable of 200 kSps conversion rate. The input  
accepts a single-ended analog input signal. On-chip buff-  
ers provide high input impedance for both the AIN input  
and the VREF+ input. This significantly reduces the drive  
requirements of signal sources and reduces errors due to  
source impedances. The CS5581 is a delta-sigma convert-  
er capable of switching multiple input channels at a high  
rate with no loss in throughput. The ADC uses a low-laten-  
cy digital filter architecture. The filter is designed for fast  
settling and settles to full accuracy in one conversion. The  
converter's 16-bit data output is in serial format, with the  
serial port acting as either a master or a slave. The convert-  
er is designed to support bipolar, ground-referenced  
signals when operated from ±2.5V analog supplies.  
‰ Single-ended Analog Input  
‰ On-chip Buffers for High Input Impedance  
‰ Conversion Time = 5 µS  
‰ Settles in One Conversion  
‰ Linearity Error = 0.0008%  
‰ Signal-to-Noise = 80 dB  
‰ S/(N + D) = 80 dB  
‰ DNL = ±0.1 LSB Max.  
‰ Simple three/four-wire serial interface  
‰ Power Supply Configurations:  
- Analog: +5V/GND; IO: +1.8V to +3.3V  
The converter can operate from an analog supply of 0-5V  
or from ±2.5V. The digital interface supports standard logic  
operating from 1.8, 2.5, or 3.3 V.  
- Analog: ±2.5V; IO: +1.8V to +3.3V  
‰ Power Consumption:  
- ADC Input Buffers On: 85 mW  
- ADC Input Buffers Off: 60 mW  
ORDERING INFORMATION:  
See Ordering Information on page 32.  
V1+  
V2+  
VL  
CS5581  
VREF+  
VREF-  
SMODE  
CS  
SERIAL  
INTERFACE  
DIGITAL  
FILTER  
LOGIC  
SCLK  
ADC  
AIN  
SDO  
RDY  
ACOM  
BUFEN  
RST  
CONV  
DIGITAL CONTROL  
OSC/CLOCK  
GENERATOR  
BP/UP  
MCLK  
V2-  
TST  
VLR3  
VLR  
VLR2  
V1-  
DCR  
This document contains information for a new product.  
Cirrus Logic reserves the right to modify this product without notice.  
Preliminary Product Information  
MAR ‘08  
DS796PP1  
Copyright © Cirrus Logic, Inc. 2008  
http://www.cirrus.com  
(All Rights Reserved)  

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