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CS5560_09 PDF预览

CS5560_09

更新时间: 2024-09-15 06:49:27
品牌 Logo 应用领域
凌云 - CIRRUS /
页数 文件大小 规格书
32页 549K
描述
±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ΔΣ ADC

CS5560_09 数据手册

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5/4/09  
CS5560  
±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ΔΣ ADC  
Features & Description  
General Description  
The CS5560 is a single-channel, 24-bit analog-to-digital  
converter capable of 50 kSps conversion rate. The input  
accepts a fully differential analog input signal. On-chip  
buffers provide high input impedance for both the AIN in-  
puts and the VREF+ input. This significantly reduces the  
drive requirements of signal sources and reduces errors  
due to source impedances. The CS5560 is a delta-sigma  
converter capable of switching multiple input channels at  
a high rate with no loss in throughput. The ADC uses a  
low-latency digital filter architecture. The filter is designed  
for fast settling and settles to full accuracy in one conver-  
sion. The converter's 24-bit data output is in serial form,  
with the serial port acting as either a master or a slave. The  
converter is designed to support bipolar, ground-refer-  
enced signals when operated from ±2.5V analog supplies.  
Differential Analog Input  
On-chip Buffers for High Input Impedance  
Conversion Time = 20 μS  
Settles in One Conversion  
Linearity Error = 0.0005%  
Signal-to-Noise = 110 dB  
24 Bits, No Missing Codes  
Simple three/four-wire serial interface  
Power Supply Configurations:  
- Analog: +5 V / GND; IO: +1.8 V to +3.3 V  
- Analog: ±2.5 V; IO: +1.8 V to +3.3 V  
The converter can operate from an analog supply of 0-5V  
or from ±2.5V. The digital interface supports standard log-  
ic operating from 1.8, 2.5, or 3.3 V.  
Power Consumption:  
- ADC Input Buffers On: 90 mW  
- ADC Input Buffers Off: 60 mW  
ORDERING INFORMATION:  
See Ordering Information on page 32.  
V1+  
V2+  
VL  
CS5560  
VREF+  
VREF-  
SMODE  
CS  
SERIAL  
INTERFACE  
DIGITAL  
FILTER  
LOGIC  
ADC  
SCLK  
SDO  
AIN+  
AI N-  
RDY  
SLEEP  
RST  
BUFEN  
DIGITAL CONTROL  
CONV  
BP/UP  
OSC/CLOCK  
GENERATOR  
MCLK  
V2-  
DCR  
VLR2  
V1-  
TST  
VLR  
This document contains information for a new product.  
Cirrus Logic reserves the right to modify this product without notice.  
Preliminary Product Information  
MAY ‘09  
DS713PP2  
Copyright Cirrus Logic, Inc. 2009  
http://www.cirrus.com  
(All Rights Reserved)  

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