CS5523

更新时间： 2024-11-15 06:49:27

品牌	Logo	应用领域
凌云 - CIRRUS		/
页数	文件大小	规格书
56页	392K
描述
16-bit or 24-bit, 2/4/8-channel ADCs with PGIA

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中文翻译

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数据手册

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CS5523 数据手册

CS5521/22/23/24/28

16-bit or 24-bit, 2/4/8-channel ADCs with PGIA

Features

General Description

The CS5521/22/23/24/28 are highly integrated ΔΣ ana-

log-to-digital converters (ADCs) which use charge-

balance techniques to achieve 16-bit (CS5521/23) and

24-bit (CS5522/24/28) performance. The ADCs come as

 Low Input Current (100 pA), Chopper-

stabilized Instrumentation Amplifier

 Scalable Input Span (Bipolar/Unipolar)

- 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V,

2.5 V, 5 V

- External: 10 V, 100 V

either

two-channel

(CS5521/22),

four-channel

(CS5523/24), or eight-channel (CS5528) devices and

include a low-input-current, chopper-stabilized instru-

mentation amplifier. To permit selectable input spans of

25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs

include a PGA (programmable gain amplifier). To ac-

 Wide V

Input Range (+1 to +5 V)

REF

 Fourth Order Delta-Sigma A/D Converter

 Easy to Use Three-wire Serial Interface Port commodate ground-based thermocouple applications,

the devices include a charge pump drive which provides

a negative bias voltage to the on-chip amplifiers.

Conversion Data FIFO

- Programmable/Auto Channel Sequencer with

- Accessible Calibration Registers per Channel

- Compatible with SPI™ and Microwire™

 System and Self Calibration

 Eight Selectable Word Rates

- Up to 617 Sps (XIN = 200 kHz)

These devices also include a fourth-order ΔΣ modulator

followed by a digital filter which provides eight selectable

output word rates. The digital filters are designed to settle

to full accuracy within one conversion cycle and when

operated at word rates below 30 Sps, they reject both

50 Hz and 60 Hz interference.

- Single Conversion Settling

These single-supply products are ideal solutions for

measuring isolated and non-isolated, low-level signals in

process control applications.

- 50/60 Hz ±3 Hz Simultaneous Rejection

 Single +5 V Power Supply Operation

- Charge Pump Drive for Negative Supply

- +3 to +5 V Digital Supply Operation

 Low Power Consumption: 6.0 mW

ORDERING INFORMATION

See page 53.

VA+

AGND

VREF+ VREF-

DGND VD+

Controller,

AIN1+

AIN1-

Setup Registers,

Channel Scan

Logic

Digital Filter

Differential

4^thOrder

ΔΣ

X20

AIN2+

AIN2-

Modulator

MUX

CS5524

Shown

AIN3+

AIN3-

Serial Port

Interface

SCLK

SDI

AIN4+

AIN4-

Data FIFO &

Calibration Registers

Clock

Gen.

Latch

SDO

NBV

CPD

A0 A1 XIN XOUT

JUL ‘09

DS317F8

http://www.cirrus.com

12 3 4 5 6 7...56

中文翻译

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与CS5523相关器件

型号	品牌	获取价格	描述	数据表
CS5523-AP	CIRRUS	获取价格	16 BIT OR 24 BIT 2/4/8 CHANNEL ADCS WITH PGIA
CS5523-AS	CIRRUS	获取价格	16 BIT OR 24 BIT 2/4/8 CHANNEL ADCS WITH PGIA
CS5523-ASZ	CIRRUS	获取价格	16-bit or 24-bit, 2/4/8-channel ADCs with PGIA
CS5524	CIRRUS	获取价格	16-bit or 24-bit, 2/4/8-channel ADCs with PGIA
CS5524-AP	CIRRUS	获取价格	16 BIT OR 24 BIT 2/4/8 CHANNEL ADCS WITH PGIA
CS5524-AS	CIRRUS	获取价格	16 BIT OR 24 BIT 2/4/8 CHANNEL ADCS WITH PGIA
CS5524-ASZ	CIRRUS	获取价格	16-bit or 24-bit, 2/4/8-channel ADCs with PGIA
CS5525	CIRRUS	获取价格	16 BIT / 20 BIT MULTI RANGE ADC WITH 4 BIT LATCH
CS5525_05	CIRRUS	获取价格	16-bit/20-bit, Multi-range ADC with 4-bit Latch
CS5525-AP	CIRRUS	获取价格	16 BIT / 20 BIT MULTI RANGE ADC WITH 4 BIT LATCH

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