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CS5522 PDF预览

CS5522

更新时间: 2024-02-28 14:08:56
品牌 Logo 应用领域
凌云 - CIRRUS /
页数 文件大小 规格书
56页 868K
描述
16-bit or 24-bit, 2/4/8-channel ADCs with PGIA

CS5522 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP, SSOP20,.3针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.59
最大模拟输入电压:5.25 V最小模拟输入电压:-1.8 V
转换器类型:ADC, DELTA-SIGMAJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:7.2 mm
最大线性误差 (EL):0.0015%湿度敏感等级:3
模拟输入通道数量:2位数:24
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3/5,5 V认证状态:Not Qualified
座面最大高度:2.13 mm子类别:Other Converters
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:5.3 mm
Base Number Matches:1

CS5522 数据手册

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CS5521/22/23/24/28  
16-bit or 24-bit, 2/4/8-channel ADCs with PGIA  
Features  
General Description  
The CS5521/22/23/24/28 are highly integrated ∆Σ ana-  
log-to-digital converters (ADCs) which use charge-  
balance techniques to achieve 16-bit (CS5521/23) and  
24-bit (CS5522/24/28) performance. The ADCs come as  
z Low Input Current (100 pA), Chopper-  
stabilized Instrumentation Amplifier  
z Scalable Input Span (Bipolar/Unipolar)  
- 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V,  
2.5 V, 5 V  
- External: 10 V, 100 V  
either  
two-channel  
(CS5521/22),  
four-channel  
(CS5523/24), or eight-channel (CS5528) devices and  
include a low-input-current, chopper-stabilized instru-  
mentation amplifier. To permit selectable input spans of  
25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs  
include a PGA (programmable gain amplifier). To ac-  
z Wide V  
Input Range (+1 to +5 V)  
REF  
z Fourth Order Delta-Sigma A/D Converter  
z Easy to Use Three-wire Serial Interface Port commodate ground-based thermocouple applications,  
the devices include a charge pump drive which provides  
a negative bias voltage to the on-chip amplifiers.  
Conversion Data FIFO  
- Programmable/Auto Channel Sequencer with  
- Accessible Calibration Registers per Channel  
- Compatible with SPI™ and Microwire™  
z System and Self Calibration  
z Eight Selectable Word Rates  
- Up to 617 Sps (XIN = 200 kHz)  
These devices also include a fourth-order ∆Σ modulator  
followed by a digital filter which provides eight selectable  
output word rates. The digital filters are designed to settle  
to full accuracy within one conversion cycle and when  
operated at word rates below 30 Sps, they reject both  
50 Hz and 60 Hz interference.  
- Single Conversion Settling  
These single-supply products are ideal solutions for  
measuring isolated and non-isolated, low-level signals in  
process control applications.  
- 50/60 Hz ±3 Hz Simultaneous Rejection  
z Single +5 V Power Supply Operation  
- Charge Pump Drive for Negative Supply  
- +3 to +5 V Digital Supply Operation  
z Low Power Consumption: 6.0 mW  
ORDERING INFORMATION  
See page 52.  
VA+  
AGND  
VREF+ VREF-  
DGND VD+  
X1  
Controller,  
X1  
AIN1+  
AIN1-  
Setup Registers,  
&
Channel Scan  
Logic  
Digital Filter  
Differential  
4th Order  
∆Σ  
+
X20  
AIN2+  
AIN2-  
Modulator  
X1  
MUX  
CS5524  
Shown  
AIN3+  
AIN3-  
CS  
Serial Port  
Interface  
SCLK  
SDI  
AIN4+  
AIN4-  
Data FIFO &  
Calibration Registers  
Clock  
Gen.  
Latch  
SDO  
NBV  
CPD  
A0 A1 XIN XOUT  
JUL ‘08  
DS317F6  
Copyright © Cirrus Logic, Inc. 2008  
http://www.cirrus.com  
(All Rights Reserved)  

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