Datasheet > CS5321-BLZ

CS5321-BLZ

更新时间： 2024-09-28 22:40:19

品牌	Logo	应用领域
凌云 - CIRRUS		转换器
页数	文件大小	规格书
36页	654K
描述
24-bit, Variable-bandwidth A/D Converter Chipset

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数据手册

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CS5321-BLZ 数据手册

CS5321/22

24-bit, Variable-bandwidth A/D Converter Chipset

Features

Description

The CS5321/CS5322 chipset functions as a unique

A/D converter intended for very high-resolution

measurement of signals below 1600 Hz. It is specif-

ically designed for applications that require both a

high dynamic range and a low total harmonic distor-

tion. The chipset performs sampling, A/D

conversion, and anti-alias filtering.

z CMOS A/D Converter Chipset

z Dynamic Range

- 130 dB @ 25 Hz Bandwidth

- 121 dB @ 411 Hz Bandwidth

z Delta-sigma Architecture

- Fourth-order Modulator

- Variable Oversampling: 64X to 4096X

- Internal Track-and-hold Amplifier

The CS5321 uses Delta-Sigma modulation to pro-

duce highly accurate conversions. The ∆Σ

modulator oversamples, virtually eliminating the

need for external analog anti-alias filters. The

CS5322 linear-phase FIR digital filter decimates the

output to any one of seven selectable update peri-

ods: 16, 8, 4, 2, 1, 0.5, and 0.25 milliseconds. Data

is output from the digital filter in a 24-bit serial

format.

z CS5321 Signal-to-distortion: 115 dB

z Clock-jitter-tolerant Architecture

z Input Voltage Range: +4.5 V

z Flexible Filter Chip

- Hardware- or Software-selectable Options

- Seven Selectable Filter Corners (-3 dB)

Frequencies: 25, 51, 102, 205, 411, 824 and

1650 Hz

ORDERING INFORMATION

z Low Power Dissipation: <100 mW

See page 36.

CS5321

CS5322

ss2

VD+

SYNC CLKIN CS R/W

dd1

ss1

dd2

LPWR

OFST

RESET

RSEL

SCLK

SID

MSYNC

SOD

MFLG

MCLK

AINR

AIN+

Digital

Filter

ERROR

DRDY

ORCAL

DECA

DECB

DECC

Analog

Modulator

MDATA

AIN-

MDATA

HBR

VD+

DGND

CSEL

VREF+

VREF-

AGND

DGND

H/S TDATA PWDN USEOR DGND

SEP ‘05

DS454F2

http://www.cirrus.com

12 3 4 5 6 7...36

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