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CS5165AGDWR16G PDF预览

CS5165AGDWR16G

更新时间： 2024-09-19 04:37:27
品牌 Logo 应用领域
安森美 - ONSEMI 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
页数 文件大小 规格书
18页 497K
描述
5−Bit Synchronous CPU Buck Controller

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中文翻译

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CS5165AGDWR16G 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.19Is Samacsys：N
模拟集成电路 - 其他类型：SWITCHING CONTROLLER控制模式：CURRENT/VOLTAGE-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：14 V
最小输入电压：8 VJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
湿度敏感等级：3功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：最大输出电流：0.015 A
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：PUSH-PULL最大切换频率：1000 kHz
温度等级：COMMERCIAL端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

CS5165AGDWR16G 数据手册

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CS5165A  
5−Bit Synchronous CPU  
Buck Controller  
The CS5165A synchronous 5−bit NFET buck controller is  
optimized to manage the power of the next generation Pentium II  
2
processors. It’s V t control architecture delivers the fastest transient  
response (100 ns), and best overall voltage regulation in the industry  
today. It’s feature rich design gives end users the maximum flexibility  
to implement the best price/performance solutions for their end  
products.  
http://onsemi.com  
MARKING  
DIAGRAM  
The CS5165A has been carefully crafted to maximize performance and  
protect the processor during operation. It has a 5−bit DAC on board that  
holds a 1.0% tolerance over temperature. Its on board programmable  
Soft−Start insures a control startup, and the FET nonoverlap circuitry  
ensures that both FETs do not conduct simultaneously.  
The on board oscillator can be programmed up to 1.0 MHz to give  
the designer maximum flexibility in choosing external components  
and setting systems costs.  
16  
16  
SO−16WB  
DW SUFFIX  
CASE 751G  
CS5165A  
AWLYYWWG  
1
1
The CS5165A protects the processor during potentially catastrophic  
events like overvoltage (OVP) and short circuit. The OVP feature is  
part of the V architecture and does not require any additional  
CS5165A  
A
WL  
YY  
WW  
G
= Device Code  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
2
components. During short circuit, the controller pulses the MOSFETs  
in a “hiccup” mode (3.0% duty cycle) until the fault is removed. With  
this method, the MOSFETs do not overheat or self destruct.  
The CS5165A is designed for use in both single processor desktop and  
multiprocessor workstation and server applications. The CS5165A’s  
current sharing capability allows the designer to build multiple parallel  
and redundant power solutions for multiprocessor systems.  
The CS5165A contains other control and protection features such as  
Power Good, ENABLE, and adaptive voltage positioning. It is  
available in a 16 lead SOIC wide body package.  
PIN CONNECTIONS  
1
16  
V
FB  
COMP  
LGND  
PWRGD  
GATE(L)  
PGND  
V
V
V
V
ID0  
ID1  
ID2  
ID3  
Features  
2
• V Control Topology  
• Dual N−Channel Design  
SS  
• 100 ns Controller Transient Response  
• Excess of 1.0 MHz Operation  
• 5−Bit DAC with 1.0% Tolerance  
• Power Good Output With Internal Delay  
• Enable Input Provides Micropower Shutdown Mode  
• 5.0 V and 12 V Operation  
V
ID4  
C
OFF  
GATE(H)  
ENABLE  
V
CC  
ORDERING INFORMATION  
• Adaptive Voltage Positioning  
• Remote Sense Capability  
†
Device  
Package  
Shipping  
• Current Sharing Capability  
CS5165AGDW16  
CS5165AGDW16G  
SOIC−16  
47 Units/Rail  
47 Units/Rail  
• V Monitor  
CC  
SOIC−16  
(Pb−Free)  
• Hiccup Mode Short Circuit Protection  
• Overvoltage Protection (OVP)  
• Programmable Soft−Start  
CS5165AGDWR16  
SOIC−16 1000/Tape & Reel  
CS5165AGDWR16G SOIC−16 1000/Tape & Reel  
(Pb−Free)  
• 150 ns PWM Blanking  
• 65 ns FET Nonoverlap Time  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
• 40 ns Gate Rise and Fall Times (3.3 nF Load)  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
October, 2005 − Rev. 1  
CS5165A/D  
1234567...18

中文翻译

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