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CS5101A_06

更新时间: 2024-02-23 14:43:08
品牌 Logo 应用领域
凌云 - CIRRUS 转换器
页数 文件大小 规格书
39页 558K
描述
16-bit, 100 kSps / 20 kSps A/D Converters

CS5101A_06 数据手册

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CS5101A  
CS5102A  
16-bit, 100 kSps / 20 kSps A/D Converters  
Features  
Description  
The CS5101A and CS5102A are 16-bit monolithic  
CMOS analog-to-digital converters (ADCs) capable of  
100 kSps (5101A) and 20 kSps (5102A) throughput. The  
CS5102A’s low power consumption of 44mW, coupled  
with a power-down mode, makes it particularly suitable  
for battery-powered operation.  
z Monolithic CMOS A/D Converters  
– Inherent Sampling Architecture  
– 2-channel Input Multiplexer  
– Flexible Serial Output Port  
On-chip self-calibration circuitry achieves nonlinearity of  
±0.001% of FS and guarantees 16-bit, no missing codes  
over the entire specified temperature range. Superior lin-  
earity also leads to 92 dB S/(N+D) with harmonics below  
-100 dB. Offset and full-scale errors are minimized dur-  
ing the calibration cycle, eliminating the need for external  
trimming.  
z Ultra-low Distortion  
– S/(N+D): 92 dB  
– TDH: 0.001%  
z Conversion Time  
– CS5101A: 8µs  
The CS5101A and CS5102A each consist of a 2-chan-  
nel input multiplexer, DAC, conversion and calibration  
microcontroller, clock generator, comparator, and serial  
communications port. The inherent sampling architec-  
ture of the device eliminates the need for an external  
track-and-hold amplifier.  
– CS5102A: 40 µs  
z Linearity Error: ±0.001% FS  
– Guaranteed No Missing Codes  
z Self-calibration Maintains Accuracy  
The converters’ 16-bit data is output in serial form with  
either binary or two’s complement coding. Three output  
timing modes are available for easy interfacing to micro-  
controllers and shift registers. Unipolar and bipolar input  
ranges are digitally selectable  
– Accurate Over Time & Temperature  
z Low Power Consumption  
– CS5101A: 320 mW  
– CS5102A: 44 mW  
ORDERING INFORMATION  
See “Ordering Information” on page 38.  
I
TRK1  
8
SSH/SDL  
11  
HOLD SLEEPRST STBYCODEBP/UP CRS/FIN  
12 28 16 17 10  
TRK2  
9
SDATA  
15  
2
5
3
4
14  
CLKIN  
XOUT  
Clock  
Generator  
SCLK  
Control  
21  
20  
19  
REFBUF  
Calibration  
SRAM  
Microcontroller  
-
+
VREF  
26  
27  
TEST  
AIN1  
16-Bit Charge  
Redistribution  
DAC  
-
+
SCKMOD  
-
+
24  
13  
AIN2  
18  
Comparator  
OUTMOD  
-
CH1/2  
+
22  
AGND  
25  
23  
VA-  
6
1
7
VA+  
DGND  
VD-  
VD+  
Copyright © Cirrus Logic, Inc. 2006  
JAN ‘06  
DS45F6  
http://www.cirrus.com  
(All Rights Reserved)  

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