Datasheet > CS48500

CS48500

更新时间： 2024-09-29 04:06:51

品牌	Logo	应用领域
凌云 - CIRRUS		/
页数	文件大小	规格书
28页	308K
描述
Cost-effective, High-performance 32-bit DSP

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CS48500 数据手册

CS48500 Data Sheet

Differentiating from the legacy Cirrus multi-standard, multi-

channel decoders, this new CS48500 family is still based on

the same high-performance 32-bit fixed point DSP Digital

Signal Processor core but instead is equipped with much less

memory, tailoring it for more cost-effective applications

associated with multi-channel and virtual-channel sound

enhancements. Target applications are:

FEATURES

Cost-effective, High-performance 32-bit DSP

—

300,000,000 MAC/S (multiply accumulates per second)

Dual MAC cycles per clock

72-bit accumulators are the most accurate in the industry

24k x 32 SRAM, 2k blocks - assignable to data or program

Internal ROM contains a variety of configurable sound

enhancement feature sets

—

Digital Televisions

Multimedia Peripherals

—

iPod^®Docking Stations

—

8-channel internal DMA

Automotive Head Units

Internal watch-dog DSP lock-up prevention

Automotive Outboard Amplifiers

HD-DVD & Blu-ray Disc DVD Receivers

PC Speakers

DSP Tool Set w/ Private Keys for Protecting Customer IP

Configurable Serial Audio Inputs/Outputs

In these applications there are a wide variety of licensable DSP

IP codes available today from:

—

Configurable for all input/output types

Maximum 32-bit @ 192 kHz

Supports 32-bit audio sample I/O between DSP chips

TDM input modes (multiple channels on same line)

192 kHz SPDIF transmitter

Multi-channel DSD direct stream digital SACD input

Supports Two Different Input Fs Sample Rates

—

Output can be master or slave

Cirrus also has developed, or is developing their own royalty-

free versions of popular features sets like Cirrus Bass

Manager, Cirrus Dynamic Volume Leveler, Cirrus Original

Multichannel Surround, Cirrus Virtual Speaker & Cirrus 3D-

Audio.

Dual processing path capability

Input supports dual domain slave clocking

Hardware assist time sampling for sample rate conversion

Integrated Clock Manager/PLL

—

Can operate from external crystal, external oscillator

The CS48500 is programmed using the Cirrus proprietary DSP

Composer™ GUI development tool. Processing chains may

be designed using a drag-and-drop interface to place/utilize

functional macro audio DSP primitives. The end result is a

software image that is down-loaded to the DSP via serial host

or serial boot modes.

Input Fs Auto Detection

Host & Boot via Serial Interface

Configurable GPIOs and External Interrupt Input

1.8V Core / 3.3V I/O that are +5V Tolerant

Low-power Mode

Ordering Information:

See page 23 for ordering information

—

"Energy-Star Ready" via low-power mode, 350uW in standby

Serial

Control 1

GPIO

Debug

12 Ch. Audio In /

6 Ch. SACD In

Watchdog

TMR1

32-bit

DSP

TMR2

S/PDIF

12 Ch PCM

Audio Out

PLL

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Advance Product Information

DEC ’06

DS734A3

CONFIDENTIAL

http://www.cirrus.com

12 3 4 5 6 7...28

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与CS48500相关器件

型号	品牌	获取价格	描述	数据表
CS48520	CIRRUS	获取价格	Cost-effective, High-performance 32-bit DSP
CS48520-CQZ	CIRRUS	获取价格	32-bit Audio Decoder DSP Family
CS48540	CIRRUS	获取价格	高性能、低成本的 32 位音频处理器
CS48540-CQZ	CIRRUS	获取价格	32-bit Audio Decoder DSP Family
CS48540-DQZ	CIRRUS	获取价格	32-bit Audio Decoder DSP Family
CS48560	CIRRUS	获取价格	高性能、低成本的 32 位音频处理器
CS48560-CQZ	CIRRUS	获取价格	32-bit Audio Decoder DSP Family
CS48560-CQZR	CIRRUS	获取价格	暂无描述
CS48560-DQZ	CIRRUS	获取价格	32-bit Audio Decoder DSP Family
CS485XX	CIRRUS	获取价格	32-bit Audio Decoder DSP Family

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