CS470xx Data Sheet
The CS470xx family is a new generation of audio system-on-
a-chip (ASOC) processors targeted at high fidelity, cost
sensitive designs. Derived from the highly successful
CS48500 32-bit fixed point audio enhancement processor
family, the CS470xx further simplifies system design and
reduces total system cost by integrating the S/PDIF Rx,
S/PDIF Tx, analog inputs, analog outputs, and SRCs. For
example, a hardware SRC can down-sample a 192 kHz
S/PDIF stream to a lower Fs to reduce memory and MIPS
requirements for processing. This integration effectively
reduces the chip count from 3 to 1 which allows smaller, less
expensive board designs.
FEATURES
Cost-effective, High-performance 32-bit DSP
—
—
—
—
300,000,000 MAC/S (multiply accumulates per second)
Dual MAC cycles per clock
72-bit accumulators are the highest precision in the industry
32K x 32-bit SRAM with three 2K blocks assignable to either
Y data or program memory
Integrated DAC & ADC Functionality
†
—
8 Channels of DAC output: 108dB DR, -98dB THD+N
†
—
—
4 Channels of ADC input: 105dB DR, -98dB THD+N
Target applications are:
Integrated 5:1 analog mux feeds one stereo ADC
— Automotive Head Units & Outboard Amplifiers
— Automotive Processors & Automotive Integration Hubs
— Digital TV
— MP3 Docking Stations
— AVR and DVD RX
Configurable Serial Audio Inputs/Outputs
†
—
—
—
—
Integrated 192 kHz S/PDIF Rx
Integrated 192 kHz S/PDIF Tx
Supports 32-bit Serial Data @ 192 kHz
Supports 32-bit audio sample I/O between DSP chips
— DSP Controlled Speakers (e.g. Subwoofers, Sound
Bars)
†
—
TDM I/O modes (Up to 10/8 channels per line)
Supports Different Fs Sample Rates
The CS470xx is programmed using the simple yet powerful
†
Cirrus proprietary DSP Composer™ GUI development and
pre-production tuning tool. Processing chains may be
designed using a drag-and-drop interface to place/utilize
functional macro audio DSP primitives and custom audio
filtering blocks. The end result is a software image that is
downloaded to the DSP via serial control port.
—
—
Three integrated hardware SRC blocks
Output can be master or slave
2
—
Supports dual-domain Fs on S/PDIF vs. I S inputs
DSP Tool Set w/ Private Keys Protect Customer IP
Integrated Clock Manager/PLL
The Cirrus Framework™ programming environment offers
Assembly and C language compilers and other software
development tools for porting existing code to the CS470xx
family platform.
—
Flexibility to operate from internal PLL, external crystal,
external oscillator
Input Fs Auto Detection w/ µC Acknowledgement
Host Control & Boot via I2C™ or SPI™ Serial Interface
Configurable GPIOs and External Interrupt Input
1.8V Core and a 3.3V I/O that is tolerant to 5V input
Low-power Mode
The CS470xx is available in a 100-pin LQFP package with
exposed pad for better thermal characteristics. Both
Commercial (0°C to +70°C) and Automotive (-40°C to
+85°C) temperature grades.
Ordering Information:
See p. 33 for ordering information.
“†” Feature may differ on CS47024 or CS47028, see p. 8.
ADC’s & DAC’s operate
in Single ended or
Differential mode
Clock
Manager
DBC
PLL
Timers GPIO
(I2C Slave)
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
I2S /
TDM /
SPDIF
S
R
C
2
8ch
x4
I2S /
TDM
Crystal® 32-bit Core
in the CS47048 DSP
text
S
R
C
3
SRC3 has 8
independent Channels
for In or Out
x8
ADC0/1
8ch
DMA
S
R
C
1
ROM
Stereo Inputs
On Analog in
X
4ch
RAM
PIC
x2
ROM
RAM
I2S / TDM
ADC2/3
ROM
RAM
Y
P
x2
SPI / I2C
Control
I2S / TDM /
SPDIF
32K x 32-bit SRAM with three 2K blocks
Assignable to Program or Y Data memory
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Copyright 2009 Cirrus Logic
CONFIDENTIAL
AUG ’09
DS787PP1
http://www.cirrus.com
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