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CS47048B-DQZ PDF预览

CS47048B-DQZ

更新时间: 2024-11-16 06:49:27
品牌 Logo 应用领域
凌云 - CIRRUS 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
34页 634K
描述
Audio SOC Processor Family

CS47048B-DQZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP,
针数:100Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.71Is Samacsys:N
地址总线宽度:桶式移位器:NO
边界扫描:NO最大时钟频率:27 MHz
外部数据总线宽度:格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PQFP-G100
长度:14 mm低功率模式:YES
湿度敏感等级:3端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:COPPER端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

CS47048B-DQZ 数据手册

 浏览型号CS47048B-DQZ的Datasheet PDF文件第2页浏览型号CS47048B-DQZ的Datasheet PDF文件第3页浏览型号CS47048B-DQZ的Datasheet PDF文件第4页浏览型号CS47048B-DQZ的Datasheet PDF文件第5页浏览型号CS47048B-DQZ的Datasheet PDF文件第6页浏览型号CS47048B-DQZ的Datasheet PDF文件第7页 
CS47048 Data Sheet  
FEATURES  
The CS47048 family is a new generation of audio system-on-a-  
chip (ASOC) processors targeted at high fidelity, cost sensitive  
designs. Derived from the highly successful CS48500 32-bit  
fixed point audio enhancement processor family, the CS47048  
further simplifies system design and reduces total system cost  
by integrating the S/PDIF Rx, S/PDIF Tx, analog inputs, analog  
outputs, and SRCs to simplify system design. For example, a  
hardware SRC can down-sample a 192kHz S/PDIF stream to a  
lower Fs to reduce memory and MIPS requirements for  
processing. This integration effectively reduces the chip count  
from 3 to 1 which allows smaller, less expensive board designs.  
‰ Cost-effective, High-performance 32-bit DSP  
300,000,000 MAC/S (multiply accumulates per second)  
Dual MAC cycles per clock  
72-bit accumulators are the most accurate in the industry  
32K x 32-bit SRAM with three 2K blocks assignable to either  
Y data or program memory.  
‰ Integrated DAC & ADC Functionality  
8 Channels of DAC output: 108dB DR, 98dB THD+N  
4 Channels of ADC input: 105dB DR, 98dB THD+N  
Integrated 5:1 analog mux feeds one stereo ADC  
Target applications are:  
— Automotive Head Units & Outboard Amplifiers  
— Automotive Processors & Automotive Integration Hubs  
— Digital TV  
‰ Configurable Serial Audio Inputs/Outputs  
Integrated 192 kHz S/PDIF Rx  
— MP3 Docking Stations  
— AVR and DVD RX  
— DSP Controlled Speakers (e.g. Subwoofers, Sound  
Bars)  
Integrated 192 kHz S/PDIF Tx  
Supports 32-bit Serial Data @ 192 kHz  
Supports 32-bit audio sample I/O between DSP chips  
TDM I/O modes (Up to 8 channels per line)  
The CS47048 is programmed using the simple yet powerful  
‰ Supports Different Fs Sample Rates  
Cirrus proprietary DSP ComposerGUI development and pre-  
production tuning tool. Processing chains may be designed  
using a drag-and-drop interface to place/utilize functional  
macro audio DSP primitives and custom audio filtering blocks.  
The end result is a software image that is downloaded to the  
DSP via serial control port.  
Three Integrated hardware SRC blocks  
Output can be master or slave  
2
Supports dual-domain Fs on inputs (S/PDIF Rx and I S)  
2
Supports dual-domain Fs on outputs (S/PDIF Tx and I S)  
DSP programming could not be easier for the novice or small  
engineering development group. DSP Composer provides the  
programmer with faster time-to-market opportunities and the  
ability to implement custom code.  
‰ DSP Tool Set w/ Private Keys Protect Customer IP  
‰ Integrated Clock Manager/PLL  
Flexibility to operate from internal PLL, external crystal,  
external oscillator  
The CS47048 is available in a 100-pin LQFP package with  
exposed pad for better thermal characteristics. Both  
‰ Input Fs Auto Detection w/ µC Acknowledgement  
‰ Host & Boot via SPI / I2C Serial Interface  
‰ Configurable GPIOs and External Interrupt Input  
‰ 1.8V Core and a 3.3V I/O that is tolerant to 5V input  
‰ Low-power Mode: 620µW  
Commercial (0°C to +70°C) and Automotive (-40°C to +85°C)  
temperature grades.  
Ordering Information:  
See page 30 for ordering information  
ADC’s & DAC’s operate  
in Single ended or  
Differential mode  
Clock  
Manager  
DBC  
PLL  
Timers GPIO  
(I2C Slave)  
DAC0  
DAC1  
I2S /  
TDM /  
SPDIF  
DAC2  
S
DAC3  
DAC4  
DAC5  
DAC6  
DAC7  
R
C
2
8ch  
x4  
I2S /  
TDM  
Coyote32  
32-bit DSP  
SRC3 has 8  
independent Channels  
for In or Out  
S
R
C
3
x8  
ADC0/1  
8ch  
DMA  
PIC  
ROM  
RAM  
S
R
C
1
ROM  
RAM  
Stereo Inputs  
On Analog in  
X
4ch  
x2  
ROM  
RAM  
I2S / TDM  
ADC2/3  
Y
P
x2  
SPI / I2C  
Control  
I2S / TDM /  
SPDIF  
32K x 32-bit SRAM with three 2K blocks  
Assignable to Program or Y Data memory  
This document contains information for a new product.  
Cirrus Logic reserves the right to modify this product without notice.  
Advance Product Information  
Copyright 2008 Cirrus Logic  
CONFIDENTIAL  
OCT ’08  
DS787A7  
http://www.cirrus.com  

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