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CS235GN18

更新时间： 2024-02-15 20:48:23
品牌 Logo 应用领域
樱桃 - CHERRY 模拟IC光电信号电路光电二极管
页数 文件大小 规格书
6页 151K
描述
System Photoelectric Smoke Detector

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中文翻译

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CS235GN18 技术参数

生命周期：Transferred零件包装代码：DIP
包装说明：,针数：18
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.09Is Samacsys：N
其他特性：ALSO OPERATES ON 12V SUPPLY模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-PDIP-T18功能数量：1
端子数量：18最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified最大供电电压 (Vsup)：35 V
最小供电电压 (Vsup)：13.8 V标称供电电压 (Vsup)：22.5 V
表面贴装：NO温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子位置：DUAL
Base Number Matches：1

CS235GN18 数据手册

 浏览型号CS235GN18的Datasheet PDF文件第2页浏览型号CS235GN18的Datasheet PDF文件第3页浏览型号CS235GN18的Datasheet PDF文件第4页浏览型号CS235GN18的Datasheet PDF文件第5页浏览型号CS235GN18的Datasheet PDF文件第6页 
CS235  
System Photoelectric Smoke Detector  
Features  
Description  
The CS235 System Smoke Detector  
are amplifiers A1 and A2, syn-  
chronous detector, voltage com-  
parator and the decode counter.  
The voltage gain of A2 and the  
comparator reference voltage are  
■ Synchronous Detection  
is a photo electric type with a  
pulsed infrared LED as the light  
source and a silicon photodiode as  
the light detector. The CS235 IC,  
for High Noise Immunity  
■ Pulsed Operation for Low  
Average Current Drain  
along with passive external compo- set by external resistors.  
nents, controls the system timing  
■ System Gain Externally  
Set  
Additional on-chip features include  
and signal processing.  
an ICC current limiter. The current  
limiter eliminates power-on false  
alarming.  
■ System Sensitivity  
Low average current is attained by  
pulsing the system once every 10  
seconds for 20 milliseconds. Bias is  
applied to the signal processing cir-  
cuitry for this time interval. During  
the second half of the pulse, the last  
10 milliseconds, the IR LED is  
pulsed and the unit samples for an  
alarm level smoke condition. After  
the first alarm level signal the sam-  
ple rate increases to a two second  
interval. After three consecutive  
alarm level samples the logic drives  
the output latch signalling the sys-  
tem panel.  
Externally Adjustable  
■ System Operation  
Monitored by Means of  
External Red LED  
The oscillator controls the IR LED  
excitation frequency and provides  
drive to the synchronous detector.  
The synchronous detection method  
has very high noise rejection perfor-  
mance.  
The internal latch is capable of sink-  
ing 100 milliamps maximum and  
will clamp the VCC pin to 5 volts  
when tripped. The latch current is  
determined by an external resistor  
typically located in the master  
panel and is reset by temporary  
removal of detector power.  
Package Options  
18 Lead PDIP & SOIC Wide  
Timer  
The signal processing circuit blocks  
1
2
3
4
5
6
7
8
9
18  
17  
Timer Cap  
Pulse Width  
Timer Period  
Program  
ICC Program  
V
CC /Output  
16 V REG  
Block Diagram  
Hi Level GND  
A1 Input (-)  
A1 Input (+)  
LO Level GND  
A2 Input  
15 LED Output  
Oscillator  
Program  
Internal Bias  
14  
PULSE  
WIDTH  
INT OSC TIMER PGM  
BIAS PGM CAP RES  
LED H.L. VR ICC VCC  
/
13  
12  
11  
10  
Gnd  
PGM OUT  
NC  
Detector Output  
POWER  
UP  
CURRENT  
LIMITER  
MAIN  
A2 Output  
Detector  
Reference  
GATE  
TIMER  
LED  
DRIVER  
OUTPUT  
LATCH  
OSCILLATOR  
CLOCK  
GATE BIAS  
POWER UP BIAS  
SET  
A1 IN  
(-)  
SYNC  
DETECTOR  
COUNTER  
COMP  
A1  
¥
Ð3  
A2  
¥
A1 IN  
(+)  
DET  
OUT  
A2  
OUT  
DET  
REF  
L.L.  
GND  
A2  
IN  
NC  
Cherry Semiconductor Corporation  
2000 South County Trail, East Greenwich, RI 02818  
Tel: (401)885-3600 Fax: (401)885-5786  
Email: info@cherry-semi.com  
Web Site: www.cherry-semi.com  
Rev. 7/6/98  
1
A
Company  
¨
123456

中文翻译

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