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CS230002-CZZ PDF预览

CS230002-CZZ

更新时间: 2024-01-06 13:11:42
品牌 Logo 应用领域
凌云 - CIRRUS 时钟
页数 文件大小 规格书
3页 84K
描述
1x, 2x, 4x, and 8x Clock Multiplier with Internal LCO

CS230002-CZZ 数据手册

 浏览型号CS230002-CZZ的Datasheet PDF文件第2页浏览型号CS230002-CZZ的Datasheet PDF文件第3页 
CS2300-02  
1x, 2x, 4x, and 8x Clock Multiplier with Internal LCO  
Features  
Ordering Information  
 Clock Multiplier / Jitter Reduction  
The CS2300-02 is available in a 10-pin MSOP package  
in Commercial (-10°C to +70°C) grade. Customer de-  
velopment kits are also available for custom device  
prototyping and device evaluation. Please see “Order-  
ing Information” on page 2 for complete details.  
Generates a Low Jitter 6 - 75 MHz Clock  
from a Jittery 750 kHz to 30 MHz Clock  
Source  
 Internal LCO Reference Clock  
 128 Hz Loop Filter Bandwidth  
 Selectable Multiplication Factors  
Pin-Out Diagram  
1x, 2x, 4x, and 8x  
10  
9
M0  
VD  
GND  
1
2
3
4
5
 Output Enable Pin  
M1  
 Lock Indicator  
8
CLK_OUT  
LOCK  
OUT_EN  
FILTN  
FILTP  
 Minimal Board Space Required  
7
CLK_IN  
6
No External Analog Loop-filter  
Components  
Hardware Controls Settings  
General Description  
The CS2300-02 is an extremely versatile system clock-  
ing device that utilizes a programmable phase lock loop.  
The CS2300-02 is based on a hybrid analog-digital PLL  
architecture comprised of a unique combination of a  
Delta-Sigma Fractional-N Frequency Synthesizer and a  
Digital PLL. This architecture allows for generation of a  
low-jitter clock relative to an external noisy synchroniza-  
tion clock with frequencies as low as 750 kHz. The  
CS2300-02 is a CS2300-OTP device that has been pre-  
configured at the factory. There are three hardware con-  
figuration pins available for mode and feature selection.  
M1  
0
M0  
0
PLL_OUT  
1x CLK_IN  
2x CLK_IN  
4x CLK_IN  
8x CLK_IN  
0
1
1
0
1
1
OUT_EN  
CLK_OUT  
0
1
Enabled  
High Impedance  
FILTP  
0.1 µF  
LOCK  
PLL Lock  
Indicator  
LCO  
FILTN  
Fractional-N  
Frequency Synthesizer  
CLK_OUT  
6 MHz to 75 MHz  
PLL Output  
M[1:0]  
00=1x  
01=2x  
10=4x  
11=8x  
M1  
M0  
N
Ratio Selection  
Output  
Enable/Disable  
OUT_EN  
Output to Input  
Clock Ratio  
VD  
3.3 V  
128 Hz BW Digital PLL  
& Fractional N Logic  
0.1 µF  
1 µF  
CLK_IN  
750 kHz to 30 MHz  
GND  
Frequency Reference  
This document contains information for a new product.  
Cirrus Logic reserves the right to modify this product without notice.  
Advance Product Information  
Copyright © Cirrus Logic, Inc. 2008  
February '08  
PS855A1  
(All Rights Reserved)  
http://www.cirrus.com  

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