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CS2100-OTP PDF预览

CS2100-OTP

更新时间: 2024-01-26 02:10:09
品牌 Logo 应用领域
凌云 - CIRRUS 时钟
页数 文件大小 规格书
28页 516K
描述
Fractional-N Clock Multiplier

CS2100-OTP 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP, TSSOP10,.19,20Reach Compliance Code:compliant
风险等级:5.7模拟集成电路 - 其他类型:PHASE LOCKED LOOP
JESD-30 代码:S-PDSO-G10长度:3 mm
功能数量:1端子数量:10
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP10,.19,20封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:1.1 mm最大供电电流 (Isup):18 mA
最大供电电压 (Vsup):3.5 V最小供电电压 (Vsup):3.1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:HYBRID温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mmBase Number Matches:1

CS2100-OTP 数据手册

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CS2100-OTP  
Fractional-N Clock Multiplier  
Features  
General Description  
The CS2100-OTP is an extremely versatile system  
clocking device that utilizes a programmable phase lock  
loop. The CS2100-OTP is based on a hybrid analog-  
digital PLL architecture comprised of a unique combina-  
 Clock Multiplier / Jitter Reduction  
Generates a Low Jitter 6 - 75 MHz Clock  
from a Jittery or Intermittent 50 Hz to  
30 MHz Clock Source  
tion of  
a
Delta-Sigma Fractional-N Frequency  
 Highly Accurate PLL Multiplication Factor  
Synthesizer and a Digital PLL. This architecture allows  
for generation of a low-jitter clock relative to an external  
noisy synchronization clock with frequencies as low as  
50 Hz. The CS2100-OTP has many configuration op-  
tions which are set once prior to runtime. At runtime  
there are three hardware configuration pins available for  
mode and feature selection.  
Maximum Error Less Than 1 PPM in High-  
Resolution Mode  
 One-Time Programmability  
Configurable Hardware Control Pins  
Configurable Auxiliary Output  
 Flexible Sourcing of Reference Clock  
The CS2100-OTP is available in a 10-pin MSOP pack-  
age in Commercial (-10°C to +70°C) grade. Customer  
development kits are also available for custom device  
prototyping, small production programming, and device  
evaluation. Please see “Ordering Information” on  
page 28 for complete details.  
External Oscillator or Clock Source  
Supports Inexpensive Local Crystal  
 Minimal Board Space Required  
No External Analog Loop-filter  
Components  
3.3 V  
Timing Reference  
Frequency Reference  
PLL Output  
Hardware  
Hardware Configuration  
Control  
Auxiliary  
Output  
Lock Indicator  
8 MHz to 75 MHz  
Low-Jitter Timing  
Reference  
Fractional-N  
Frequency Synthesizer  
6 to 75 MHz  
PLL Output  
N
50 Hz to 30 MHz  
Frequency  
Digital PLL &  
Reference  
Fractional N Logic  
Output to Input  
Clock Ratio  
This document contains information for a new product.  
Cirrus Logic reserves the right to modify this product without notice.  
Preliminary Product Information  
Copyright © Cirrus Logic, Inc. 2008  
JUN '08  
DS841PP1  
(All Rights Reserved)  
http://www.cirrus.com  

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