Datasheet > CS2100-CP_09

CS2100-CP_09

更新时间： 2024-02-23 02:22:06

品牌	Logo	应用领域
凌云 - CIRRUS		时钟
页数	文件大小	规格书
32页	270K
描述
Fractional-N Clock Multiplier

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CS2100-CP_09 数据手册

CS2100-CP

Fractional-N Clock Multiplier

Features

General Description

 Clock Multiplier / Jitter Reduction

The CS2100-CP is an extremely versatile system

clocking device that utilizes a programmable phase

lock loop. The CS2100-CP is based on a hybrid ana-

log-digital PLL architecture comprised of a unique

combination of a Delta-Sigma Fractional-N Frequency

Synthesizer and a Digital PLL. This architecture allows

for generation of a low-jitter clock relative to an exter-

nal noisy synchronization clock at frequencies as low

as 50 Hz. The CS2100-CP supports both I²C and SPI

for full software control.

–

Generates a Low Jitter 6 - 75 MHz Clock

from a Jittery or Intermittent 50 Hz to 30

MHz Clock Source

 Highly Accurate PLL Multiplication Factor

–

Maximum Error Less Than 1 PPM in High-

Resolution Mode

 I²C™ / SPI™ Control Port

 Configurable Auxiliary Output

 Flexible Sourcing of Reference Clock

The CS2100-CP is available in a 10-pin MSOP pack-

age in Commercial (-10°C to +70°C) grade. Customer

development kits are also available for device evalua-

tion. Please see “Ordering Information” on page 32 for

complete details.

–

External Oscillator or Clock Source

Supports Inexpensive Local Crystal

 Minimal Board Space Required

–

No External Analog Loop-filter

Components

3.3 V

Timing Reference

Frequency Reference

PLL Output

I²C/SPI

Software Control

I²C / SPI

Auxiliary

Output

Lock Indicator

8 MHz to 75 MHz

Low-Jitter Timing

Reference

Fractional-N

Frequency Synthesizer

6 to 75 MHz

PLL Output

50 Hz to 30 MHz

Frequency

Digital PLL & Fractional

N Logic

Reference

Output to Input

Clock Ratio

AUG '09

DS840F1

http://www.cirrus.com

12 3 4 5 6 7...32

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