CPC5602C
N Channel Depletion Mode FET
Description
Features
The CPC5602C is an “N” channel depletion mode Field
Effect Transistor (FET) that utilizes Clare’s proprietary
third generation vertical DMOS process. The third
generation process realizes world class, high voltage
MOSFET performance in an economical silicon gate
process. The vertical DMOS process yields a highly
reliable device particularly in difficult application
environments such as telecommunications.
• Low on resistance 10 ohms
• High input impedance
• Low input and output leakage
• Small package size SOT-223
• PC Card (PCMCIA) Compatible
• PCB Space and Cost Savings
Applications
• Support Component for LITELINK TM
Data Access Arrangement (DAA)
• Normally-on switch
One of the primary applications for the CPC5602C is as
a linear regulator/ hook switch for the LITELINKTM Data
Access Arrangements (DAA) Devices (CPC5610A,
CPC5611A, CPC5604A).
• Telecom
• Constant Current Source
The CPC5602C has a typical on-resistance of 8Ω, a
breakdown voltage exceeding 350V and is available in
an SOT-223 package. As with all MOS devices, the FET
structure prevents thermal runaway and thermal-induced
secondary breakdown.
Ordering Information
Absolute Maximum Ratings
Part #
CPC5602C
Description
N-Channel Depletion Mode FET,
SOT-223 Package
Parameter
DSS Voltage
Min
—
Max
350
Units
V
V
Total Package Dissipation
Operational Temperature
Storage Temperature
—
2.5
W
OC
OC
OC
CPC5602CTR N-Channel Depletion Mode, SOT-
223 Package
-40
-40
—
+85
+125
+220
FET-TAPE and Reel (1000 units min)
Soldering Temperature
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure
of the device to the absolute maximum ratings for an ex-
tended period may degrade the device and effect its reli-
ability.
DS-CPC5602C-Rev. 1
1
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