Datasheet > CP705-D41D11

CP705-D41D11

更新时间： 2024-10-01 14:50:11

品牌	Logo	应用领域
CENTRAL		/
页数	文件大小	规格书
9页	771K
描述
75V,1A,6.25W Bare die,31.100 X 31.100 mils,Transistor-Bipolar Power (>1A)

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CP705-D41D11 数据手册

PROCESS CP705

Small Signal Transistor

PNP - High Current Transistor Chip

PROCESS DETAILS

Process

EPITAXIAL PLANAR

Die Size

31 x 31 MILS

9.0 MILS

Die Thickness

Base Bonding Pad Area

Emitter Bonding Pad Area

Top Side Metalization

Back Side Metalization

5.9 x 11.8 MILS

6.5 x 13.8 MILS

Al - 30,000Å

Au - 18,000Å

GEOMETRY

GROSS DIE PER 4 INCH WAFER

11,212

PRINCIPAL DEVICE TYPES

2N4033

CMPT4033

CXT4033

CZT4033

R4 (22-March 2010)

www.centralsemi.com

12 3 4 5 6 7...9

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CP705V-BC327	CENTRAL	获取价格	45V,500mA,625mW Bare die,31.100 X 31.100 mils,Transistor-Small Signal (<=1A)
CP705V-BC327-25	CENTRAL	获取价格	45V,500mA,625mW Bare die,31.100 X 31.100 mils,Transistor-Small Signal (<=1A)
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