Datasheet > CP323-BST52-WS

CP323-BST52-WS

更新时间： 2024-10-30 14:41:31

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CP323-BST52-WS 技术参数

PROCESS CP323

Small Signal Transistor

NPN - Darlington Transistor Chip

Central

Semiconductor Corp.

PROCESS DETAILS

Process

EPITAXIAL PLANAR

Die Size

Die Thickness

26.8 x 26.8 MILS

9.0 MILS

Base Bonding Pad Area

Emitter Bonding Pad Area

Top Side Metalization

Back Side Metalization

4.2 x 4.2 MILS

4.3 x 4.3 MILS

Al -

Au - 18,000Å

GEOMETRY

GROSS DIE PER 4 INCH WAFER

15,900

PRINCIPAL DEVICE TYPES

BSS52

BST52

145 Adams Avenue

Hauppauge, NY 11788 USA

Tel: (631) 435-1110

Fax: (631) 435-1824

www.centralsemi.com

R1 (1-August 2002)

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