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COP8SGG544D8

更新时间： 2024-11-26 23:04:39
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美国国家半导体 - NSC 比较器微控制器
页数 文件大小 规格书
62页 910K
描述
8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGG544D8 数据手册

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October 2001  
COP8SG Family  
8-Bit CMOS ROM Based and OTP Microcontrollers with  
8k to 32k Memory, Two Comparators and USART  
Erasable windowed versions (Q3) are available for use with  
a range of COP8 software and hardware development tools.  
General Description  
The COP8SG Family ROM and OTP based microcontrollers  
Family features include an 8-bit memory mapped architec-  
ture, 15 MHz CKI with 0.67 µs instruction cycle, 14 inter-  
rupts, three multi-function 16-bit timer/counters with PWM,  
™
are highly integrated COP8 Feature core devices with 8k  
to 32k memory and advanced features including Analog  
comparators, and zero external components. These single-  
chip CMOS devices are suited for more complex applica-  
tions requiring a full featured controller with larger memory,  
™
full duplex USART, MICROWIRE/PLUS , two analog com-  
parators, two power saving HALT/IDLE modes, MIWU, idle  
timer, on-chip R/C oscillator, high current outputs, user se-  
low EMI, two comparators, and  
a full-duplex USART.  
™
lectable options (WATCHDOG , 4 clock/oscillator modes,  
COP8SGx7 devices are 100% form-fit-function compatible  
OTP (One Time Programmable) versions for use in produc-  
tion or development of the COP8SGx5 ROM.  
power-on-reset), 2.7V to 5.5V operation, program code se-  
curity, and 28/40/44 pin packages.  
Devices included in this datasheet are:  
RAM  
Device  
Memory (bytes)  
8k ROM  
I/O Pins  
24/36/40  
24/36/40  
24/36/40  
24/36/40  
24/36/40  
24/36/40  
Packages  
Temperature  
(bytes)  
28 DIP/SOIC, 40 DIP,  
44 PLCC/QFP/CSP  
28 DIP/SOIC, 40 DIP,  
44 PLCC/QFP/CSP  
28 DIP/SOIC, 40 DIP,  
44 PLCC/QFP/CSP  
28 DIP/SOIC, 40 DIP,  
44 PLCC/QFP/CSP  
28 DIP/SOIC, 40 DIP,  
44 PLCC/QFP/CSP  
28 DIP/SOIC, 40 DIP,  
44 PLCC/QFP/CSP  
28 DIP/SOIC, 40 DIP,  
44 PLCC/QFP/CSP  
28 DIP, 40 DIP, 44 PLCC  
-40 to +85˚C,  
-40 to +125˚C  
-40 to +85˚C,  
-40 to +125˚C  
-40 to +85˚C,  
-40 to +125˚C  
-40 to +85˚C,  
-40 to +125˚C  
-40 to +85˚C,  
-40 to +125˚C  
-40 to +85˚C,  
-40 to +125˚C  
-40 to +85˚C,  
-40 to +125˚C  
Room Temp.  
COP8SGE5  
COP8SGG5  
COP8SGH5  
COP8SGK5  
COP8SGR5  
COP8SGE7  
256  
16k ROM  
512  
512  
512  
512  
256  
20k ROM  
24k ROM  
32k ROM  
8k OTP EPROM  
COP8SGR7  
32k OTP EPROM  
32k EPROM  
512  
512  
24/36/40  
24/36/40  
COP8SGR7-Q3  
n Fourteen multi-source vectored interrupts servicing  
— External interrupt / Timers T0 — T3  
— MICROWIRE/PLUS Serial Interface  
— Multi-Input Wake Up  
Key Features  
n Low cost 8-bit microcontroller  
n Quiet Design (low radiated emissions)  
n Multi-Input Wakeup pins with optional interrupts (8 pins)  
n Mask selectable clock options  
— Crystal oscillator  
— Crystal oscillator option with on-chip bias resistor  
— External oscillator  
— Software Trap  
— USART (2; 1 receive and 1 transmit)  
— Default VIS (default interrupt)  
n 8-bit Stack Pointer SP (stack in RAM)  
n Two 8-bit Register Indirect Data Memory Pointers  
n True bit manipulation  
— Internal R/C oscillator  
n Internal Power-On-Reset—user selectable  
n WATCHDOG and Clock Monitor Logic—user selectable  
n Eight high current outputs  
n 256 or 512 bytes on-board RAM  
n 8k to 32k ROM or OTP EPROM with security feature  
n BCD arithmetic instructions  
Peripheral Features  
n Multi-Input Wakeup Logic  
n Three 16-bit timers (T1 — T3), each with two 16-bit  
registers supporting:  
— Processor Independent PWM mode  
— External Event Counter mode  
— Input Capture mode  
CPU Features  
n Versatile easy to use instruction set  
n 0.67 µs instruction cycle time  
™
COP8 is a trademark of National Semiconductor Corporation.  
© 2001 National Semiconductor Corporation  
DS101317  
www.national.com  
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