Datasheet > CM8888

CM8888

更新时间： 2024-02-16 22:53:50

品牌	Logo	应用领域
骅讯 - CMEDIA		PC
页数	文件大小	规格书
25页	482K
描述
High-Performance PCI Express Audio Processor

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技术参数
数据手册

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CM8888 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP, SOP20,.4
针数：	20	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.81
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	长度：	12.905 mm
功能数量：	1	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP20,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	2.85 mm	子类别：	Telecom Signaling Circuits
最大压摆率：	10 mA	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	DTMF SIGNALING CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.635 mm
Base Number Matches：	1

CM8888 数据手册

Oxygen^TMExpress-series CM8888

High-Performance PCI Express Audio Processor

DESCRIPTION

FEATURES

The Oxygen Express™-series HD CM8888 is a high-

quality PCI Express multi-channel audio processor

with an Intel HD Audio specification-compatible

audio chip. It is also a controller that can link HDA

codecs or bridge high-quality I2S codecs. The

CM8888 can be built into home audio electronics or

personal computers to provide high-fidelity sound,

providing a professional audio processing center.



Compatible with PCI Express 1.1 interface, with

bus mastering and burst modes



Embedded 8051-based MCU transcodes HD Audio

commands to link various external I2S codecs

(external 4 or 8KB serial EEPROM is required)

Built-in HD Audio and I2S controllers

I2S interface sample rate supports



192K/176.4K/96K/88.2K/48K/44.1K and

16/24/32-bit resolutions

It supports up to 14 outgoing channels and 12

ingoing channels. The 14 outgoing channels are

composed of 4 playback DMA’s, including a

multi-channel DMA (32 bits, 8 channels, 192k), a

S/PDIF & HDMI DMA (each 32 bits, 2 channels,

192k), and a RTC (real-time communication) DMA

(32 bits, 2 channels, 192k) channels. The 12

ingoing channels are spread out in 3 recording

DMAs (up to 32 bits, 192k).



Integrated 192K/176.4K/96K/88.2K/48K/44.1K

and 16/24-bit S/PDIF transmitter/receiver

Supports SPI/I2C control interface



24.576MHz crystal input required with embedded

PLL for adaptive clock rate

Block Diagram

www.cmedia.com.tw

Rev. 1.1 ︱ Page 1/25

12 3 4 5 6 7...25

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