Datasheet > CM42-67025V-45

CM42-67025V-45

更新时间： 2024-11-06 17:45:55

品牌	Logo	应用领域
TEMIC		静态存储器内存集成电路
页数	文件大小	规格书
23页	257K
描述
Dual-Port SRAM, 8KX16, 45ns, CMOS, CQCC84, LCC-84

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技术参数
数据手册

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CM42-67025V-45 技术参数

生命周期：	Transferred	包装说明：	LCC-84
Reach Compliance Code：	unknown	风险等级：	5.77
最长访问时间：	45 ns	JESD-30 代码：	S-CQCC-N84
内存密度：	131072 bit	内存集成电路类型：	DUAL-PORT SRAM
内存宽度：	16	功能数量：	1
端子数量：	84	字数：	8192 words
字数代码：	8000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	8KX16	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装形状：	SQUARE	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	认证状态：	Not Qualified
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	NO LEAD	端子位置：	QUAD
Base Number Matches：	1

CM42-67025V-45 数据手册

MATRA MHS

M 67025

8 K × 16 CMOS Dual Port RAM

Introduction

The M 67025 is a very low power CMOS dual port static Using an array of eigh transistors (8T) memory cell and

RAM organised as 8192 × 16. The M 67025 is designed fabricated with the state of the art 0.65 µ lithography

to be used as a stand-alone 16 bit dual port RAM or as a named SCMOS, the M 67025 combines an extremely low

combination MASTER/SLAVE dual port for 32 bit or standby supply current (typ = 1.0 µA) with a fast access

width

systems.

The

MATRA-MHS time at 20 ns over the full temperature range. All versions

MASTER/SLAVE dual port approach in memory system offer battery backup data retention capability with a

applications results in full speed, error free operation typical power consumption at less than 5 µW.

without the need of an additional discrete logic.

For military/space applications that demand superior

Master and slave devices provide two independant ports

with separate control, address and I/O pins that permit

independant, asynchronous access for reads and writes to

any location in the memory. An automatic power down

feature controlled by CS permits the on-chip circuitry of

each port in order to enter a very low stand by power

mode.

levels of performance and reliability the M 67025 is

processed according to the methods of the latest revision

of the MIL STD 883 (class B or S) and/or ESA SCC 9000.

Features

D Fast access time : 20/25/30/35/45/55 ns

D Wide temperature range :

D Versatile pin select for master or slave :

– M/S = H for busy output flag on master

– M/S = L for busy input flag on slave

–55 °C to +125 °C

D 67025 L low power

D INT flag for port to port communication

D Full hardware support of semaphore signaling between ports

D Fully asynchronous operation from either port

D Battery back-up operation : 2 V data retention

D TTL compatible

67025 V very low power

D Separate upper byte and lower byte control for multiplexed

bus compatibility

D Expandable data bus to 32 bits or more using master/slave

chip select when using more than one device

D On chip arbitration logic

D Single 5 V ± 10 % power supply

D For 3.3 V version, please consult sales

Rev. D (29/09/95)

12 3 4 5 6 7...23

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